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Hey, im trying to add support for the classic Cyclone II (its a very very common entry board to FPGA field)
This is the board that im trying to support: https://www.ebay.com/itm/355257902298?mkcid=16…
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While undocumented by Altera/Intel, the pre-10 series bitstream compression/decompression has been RE'ed.
It would improve user experience if a compressed RBF was decompressed before sending over t…
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For users who have license for these because they purchased an fpga from the vendor, and don't necessarily have access to vcs
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Hello, I saw the issue you posted before, as shown below. I have the same problem as you did. My MC only supports DFI, but I want to verify it on xilinx MIG. I have learned some transfer processes bef…
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@GedSid habías podido armar el testbench con los IPs de altera, y conectarlos entre si para poder enviar un stream de prueba y verificar de recibirlo en el otro extremo?
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Hi,
I am using Docker to clone this repos update branch and build the Linux kernel and dtb file for my SA2 module:
```bash
docker build -t enc -f Dockerfile .
```
My Dockerfile is:
```do…
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When I try to process a test entity instantiating a `scfifo` from the `altera_mf` library I get this error.
ERROR LOG:
```
ghdl --std=08 -P=altera/ -fsynopsys test.vhdl -e test
1. Executing GHD…
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- [ ] Feature
# Description
Os botões undo e redo, localizados no canto superior direito do container principal da aplicação, não estão apresentando funcionalidade nenhuma.
# Nome
Rony Rang…
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If, in your JTAG chain, you have more than one TAP with the same IDCODE, you can only access SLD nodes on the first chain.
For example, you have two identical Altera FPGA chip, say S10s, on the jta…
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This is the first run during an upgrade from clang-tidy-8 to 13.0.0, and I see a command line arg being dumped wrong, so (long shot) that might be related.
The actual command line is:
```
/opt/…