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I think that there might be some missing dependencies in the `maia-hdl/pyproject.toml` file - I wasn't able to rebuild the Maia IP/Vivado project using the listed dependencies. I had to install `pyth…
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where can I find the verilog versions of the ztachip as Iam not familiar with the VHDL
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### Feature Description
I am currently trying to magically speed up the simulation of [dmgcpu](https://github.com/emu-russia/dmgcpu) by checking if I can get yosys to optimize out all uses of high-im…
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### Version
Yosys 0.23 (git sha1 7ce5011c2, clang 14.0.6-2 -fPIC -Os)
### On which OS did this happen?
Linux
### Reproduction Steps
When compiling verilog files separately into RTLIL files, and t…
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In Verilog, you can create an array like this: `reg[31:0] my_array[1023:0]`. You can then directly read from or write to the array. The array can also be synthesized as BRAM if you don't access it inc…
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Is there any way to express array of module (or generate syntax in verilog) in myhdl?
Array of module:
```
wire DFF_i[15:0];
wire DFF_o[15:0];
DFF d[15:0] (clk, DFF_i, DFF_o);
```
Gener…
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Hello.
I want to get my feet wet with FPGAs via Amaranth-HDL. The toolchain needs `NEXTPNR_HIMBAECHEL`.
I get this error on the `make -j$(nproc)` step all the time. I have installed `apicula` vi…
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Hi Lawrie and thanks for that great work!
As you mentioned:
> This implementation has been done from the specification, without access to any Raspberry Pi HDL. It is currently incomplete, but so…
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To reproduce:
```python
>>> from amaranth import *
>>> from amaranth.lib import data
>>> Signal(data.ArrayLayout(5, 2))[-1]
Traceback (most recent call last):
File "", line 1, in
File ".…
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code version: a87888ea72f806f05660aa1a4dd336fc5d80a6f2
```
Traceback (most recent call last):
File "/home/oleks/projects/orbtrace/./orbtrace_builder.py", line 112, in
main()
File "/hom…
retif updated
2 months ago