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In Chisel we are seeking for intrinsics for sampled value functions like `$rose` and `$stable` to use with LTL and I think it should be lowered to the `sv` dialect in CIRCT.
I noticed that there ar…
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The core generation for FPGA fails due to:
- [x] Memory initialization is generated only inside the ifndef SYNTHESIS block #4752 - -> Fixed by https://github.com/llvm/circt/issues/4752#issuecommen…
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| | |
|--------------------|----|
| Bugzilla Link | [PR48573](https://bugs.llvm.org/show_bug.cgi?id=48573) |
| Status | NEW |
| Importance | P normal |
|…
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On the bottom of https://circt.llvm.org/ it says "Nightly performance plots: https://circt.org/perf/" but this does not work. Given that the main page is at https://circt.llvm.org/ I tried https://cir…
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Presently closure is 1.3G:
```
$ nix path-info -Sh circt
/nix/store/r2hwc36mxj5s0j35491v95fks8gq91ij-circt-1.12.0-git-dd2e912 1.3G
```
Contributing factors, to look into:
* Use of static l…
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Please propose new repos on the circt discourse forum before creating them. I think this should be in the main circt repo for a variety of reasons.
Also, shouldn't we close the circt organization …
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| | |
|--------------------|----|
| Bugzilla Link | [PR47639](https://bugs.llvm.org/show_bug.cgi?id=47639) |
| Status | NEW |
| Importance | P normal |
|…
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## Motivation
Some users of ROHD are interested in adding comments to the generated output SystemVerilog to improve readability, debuggability, and traceability for complex generation flows. While i…
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The following is using https://github.com/nektos/act to run the .github workflow. Is circt supposed to be using the Arith->Arithmetic change yet? It doesn't seem so if currently linked to llvm @ 8…
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Add support for the `moore.pow*` ops in MooreToCore: https://chipsalliance.github.io/sv-tests-results/?v=circt_verilog+11.4.3+binary_op_pow