intel rohd issues - Githubissues

intel / rohd

The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.

https://intel.github.io/rohd-website

BSD 3-Clause "New" or "Revised" License

365 stars 65 forks source link

issues

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Do not generate SystemVerilog parameter syntax when there are 0 parameters

#498 mkorbel1 opened 17 hours ago
0
Add support for SystemVerilog parameter passthroughs

#497 mkorbel1 closed 2 weeks ago
0
Fix bug where unconnected array drivers may be omitted incorrectly

#496 mkorbel1 closed 1 month ago
0
Update analysis options, lint cleanup, SDK workaround removal

#495 mkorbel1 closed 1 month ago
0
Fix bug in internal array discovery during Module build

#494 mkorbel1 closed 1 month ago
0
Support VHDL

#493 mkorbel1 opened 1 month ago
0
Performance fixes: wrong collections and unmodifiable views causing inefficiencies

#492 mkorbel1 closed 1 month ago
0
Improve simulator timestamp in past errors, suggest reset, fix #490

#491 mkorbel1 closed 1 month ago
0
Update "timestamp in the past" error to suggest a Simulator reset

#490 mkorbel1 closed 1 month ago
0
Performance bug: List view wrapping a Set for `Module.subModules`

#489 mkorbel1 closed 1 month ago
0
Buggy Assertion that tends to check for submodule contained in a module

#488 sshankar4 opened 1 month ago
0
RTL to have one array-array assignment instead of bit blasted assignments

#487 sshankar4 closed 1 month ago
0
Protect `Const` from having its value modified

#486 mkorbel1 opened 2 months ago
0
`LogicNet`s, `inOut`s, and `TriStateBuffer` (support for bidirectional wires)

#485 mkorbel1 closed 1 month ago
0
Add `selectIndex` directly to `LogicArray` (and `Logic`?) to enable one-liner accesses in generated SV.

#484 mkorbel1 opened 3 months ago
0
Support negative edge-triggered `Sequential`s

#483 mkorbel1 opened 3 months ago
0
Make full array assignments compressed to 1 line (or in-lined) in generated SystemVerilog

#482 mkorbel1 closed 1 month ago
1
Avoid Module creation for Constant Gate scenarios

#481 mjayasim9 opened 3 months ago
0
Adjust CI timeout and runners

#480 mkorbel1 closed 3 months ago
0
Add better tests for simulator phasing

#479 mkorbel1 opened 3 months ago
0
Transition to using a different addition syntax for lint avoidance

#478 mkorbel1 opened 4 months ago
0
`LogicArray` ports on `Interface`s are not uniquified by `uniquify` in `connectIO`

#477 mkorbel1 closed 1 month ago
0
`PairInterface` does not accept `LogicArray`s (or anything besides `Port`)

#476 mkorbel1 closed 1 month ago
0
Refactored tick() in simulator.dart

#475 AdamRose66 closed 3 months ago
2
fix: update flutter version to the latest

#474 quekyj closed 4 months ago
0
Fix a bug where array port element naming collisions with port names caused misconnections

#473 mkorbel1 closed 4 months ago
0
Allow immediate scheduling of an action within the same delta cycle

#472 AdamRose66 closed 4 months ago
6
Rohme interop

#471 AdamRose66 closed 4 months ago
1
Fixed point support

#470 samimia-swks opened 5 months ago
3
Static analysis for combinational loops

#469 mkorbel1 opened 5 months ago
0
Simulator upgrades for rohme compatibility (registering now and cancelling)

#468 AdamRose66 closed 5 months ago
3
Fix documentation generation

#467 mkorbel1 closed 5 months ago
0
Refractor Riverpod state management to Bloc state management

#466 quekyj opened 5 months ago
0
Trace for driver of a signal

#465 quekyj opened 5 months ago
0
Signal to code navigation

#464 quekyj opened 5 months ago
0
Update analysis options and doc checks for Dart 3.3.0

#463 mkorbel1 closed 5 months ago
0
Hierarchy Viewer need to click refresh button and then click on the signal to refresh the value

#462 quekyj opened 5 months ago
0
chore(devtool): build devtool artifact and commit to other branch

#461 quekyj closed 4 months ago
3
Add youtube channel link to Readme.md

#460 quekyj closed 6 months ago
0
Make conditional assign a little more optimistic with invalid values

#459 mkorbel1 closed 6 months ago
0
Fix bugs in `LogicStructure` instrumentation calls to `packed` and `changed` issues across `Simulator.reset`

#458 mkorbel1 closed 6 months ago
0
Non-synthesizable APIs on `LogicStructure` rely on `packed`

#457 mkorbel1 closed 6 months ago
0
Issue #377: assign a logic subset to logic (array)

#456 RPG-coder-intc closed 4 months ago
4
Make `Simulator.endSimulation` return a `Future`

#455 mkorbel1 closed 6 months ago
0
Fix defaultNextState diagram generation in FSM

#454 mkorbel1 closed 6 months ago
0
Update some pages of the user guide

#453 mkorbel1 closed 6 months ago
0
Update default permissions in GH actions

#452 mkorbel1 closed 6 months ago
0
Add a way to run the Simulator "until" a certain time (without ending the simulation)

#451 mkorbel1 opened 6 months ago
0
Add a utility for "waiting" a certain amount of time in the Simulator.

#450 mkorbel1 opened 6 months ago
0
Update counter example to be simpler and a better reference

#448 mkorbel1 closed 7 months ago
0