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intel
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rohd
The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
https://intel.github.io/rohd-website
BSD 3-Clause "New" or "Revised" License
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67
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`LogicArray` ports on `Interface`s are not uniquified by `uniquify` in `connectIO`
#477
mkorbel1
closed
4 months ago
0
`PairInterface` does not accept `LogicArray`s (or anything besides `Port`)
#476
mkorbel1
closed
4 months ago
0
Refactored tick() in simulator.dart
#475
AdamRose66
closed
6 months ago
2
fix: update flutter version to the latest
#474
quekyj
closed
6 months ago
0
Fix a bug where array port element naming collisions with port names caused misconnections
#473
mkorbel1
closed
7 months ago
0
Allow immediate scheduling of an action within the same delta cycle
#472
AdamRose66
closed
7 months ago
6
Rohme interop
#471
AdamRose66
closed
7 months ago
1
Fixed point support
#470
samimia-swks
opened
7 months ago
3
Static analysis for combinational loops
#469
mkorbel1
opened
7 months ago
0
Simulator upgrades for rohme compatibility (registering now and cancelling)
#468
AdamRose66
closed
7 months ago
3
Fix documentation generation
#467
mkorbel1
closed
7 months ago
0
Refractor Riverpod state management to Bloc state management
#466
quekyj
opened
7 months ago
0
Trace for driver of a signal
#465
quekyj
opened
7 months ago
0
Signal to code navigation
#464
quekyj
opened
7 months ago
0
Update analysis options and doc checks for Dart 3.3.0
#463
mkorbel1
closed
7 months ago
0
Hierarchy Viewer need to click refresh button and then click on the signal to refresh the value
#462
quekyj
opened
8 months ago
0
chore(devtool): build devtool artifact and commit to other branch
#461
quekyj
closed
7 months ago
3
Add youtube channel link to Readme.md
#460
quekyj
closed
8 months ago
0
Make conditional assign a little more optimistic with invalid values
#459
mkorbel1
closed
9 months ago
0
Fix bugs in `LogicStructure` instrumentation calls to `packed` and `changed` issues across `Simulator.reset`
#458
mkorbel1
closed
9 months ago
0
Non-synthesizable APIs on `LogicStructure` rely on `packed`
#457
mkorbel1
closed
9 months ago
0
Issue #377: assign a logic subset to logic (array)
#456
RPG-coder-intc
closed
7 months ago
4
Make `Simulator.endSimulation` return a `Future`
#455
mkorbel1
closed
9 months ago
0
Fix defaultNextState diagram generation in FSM
#454
mkorbel1
closed
9 months ago
0
Update some pages of the user guide
#453
mkorbel1
closed
9 months ago
0
Update default permissions in GH actions
#452
mkorbel1
closed
9 months ago
0
Add a way to run the Simulator "until" a certain time (without ending the simulation)
#451
mkorbel1
opened
9 months ago
0
Add a utility for "waiting" a certain amount of time in the Simulator.
#450
mkorbel1
opened
9 months ago
0
Update counter example to be simpler and a better reference
#448
mkorbel1
closed
9 months ago
0
Pipeline fixes and improvements
#447
mkorbel1
closed
9 months ago
0
Simulation Bug: WaveDumper Function Must Be Placed Before Simulator Class to Prevent Errors
#446
quekyj
opened
10 months ago
0
Support compiling ROHD to JavaScript
#445
mkorbel1
closed
10 months ago
0
Improve lint avoidance for width expansion
#444
mkorbel1
opened
10 months ago
2
Optimize performance of `Combinational.ssa` driver search
#443
mkorbel1
closed
10 months ago
0
Absolute value
#442
dmetis
closed
9 months ago
0
Allow constant Z driving to show up in SV without error
#441
mkorbel1
closed
10 months ago
0
More module and signal naming improvements
#440
mkorbel1
closed
10 months ago
0
Signal naming improvements
#439
mkorbel1
closed
11 months ago
0
Get a Logic of a Logic List via an index
#438
RPG-coder-intc
closed
10 months ago
1
Vscode extension
#437
quekyj
opened
11 months ago
0
Add support for edalize
#436
mkorbel1
opened
11 months ago
0
ROHD Module Hierarchy and Signals Visualization (Flutter UI)
#435
quekyj
closed
8 months ago
0
Allow `SynthBuilder` to accept multiple `Module`s.
#434
mkorbel1
opened
11 months ago
0
`PairInterface` should enable receiving/driving all sub-interfaces as well
#433
mkorbel1
opened
11 months ago
0
Add capability to `PairInterface` to modify naming at time of `addSubInterface`
#432
mkorbel1
opened
11 months ago
0
Add a quick way to instantiate simple external SystemVerilog modules.
#431
mkorbel1
opened
11 months ago
0
Improve documentation on instantiating SystemVerilog modules
#430
mkorbel1
opened
11 months ago
0
Avoid module creation for simple constant scenarios in gates
#429
mkorbel1
opened
11 months ago
3
Simulator optimization: don't simulate signals that don't matter (optionally)
#428
mkorbel1
opened
11 months ago
0
Add capabilities to transpose `LogicArray`s
#427
mkorbel1
opened
11 months ago
0
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