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intel
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rohd
The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
https://intel.github.io/rohd-website
BSD 3-Clause "New" or "Revised" License
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Add example on how to use Logic Array assignment would be good
#426
quekyj
opened
11 months ago
2
Pipeline must provide access to inputs of a given stage.
#424
kimmeljo
opened
1 year ago
6
Fix bug where generated SV has lint issues with plus and shift-left due to SV width expansion
#423
mkorbel1
closed
1 year ago
0
Logic value test improvement and minor fixes
#422
mjayasim9
closed
10 months ago
1
Allow multiple nonblocking assignments, fix #321
#421
mkorbel1
closed
1 year ago
0
Sort ports and internal signals, fix #395
#420
mkorbel1
closed
1 year ago
0
`Logic.zeroExtend` should return `this` if `width` is the same as `newWidth`, and `Swizzle` optimization in SV generation
#419
mkorbel1
opened
1 year ago
1
Update to use new runners in github actions
#417
mkorbel1
closed
6 months ago
0
Mark inputs as protected in `Module`
#416
mkorbel1
closed
1 year ago
0
Allow deploy docs (temporary PR)
#415
mkorbel1
closed
1 year ago
0
Updates to FSM and Pipeline abstractions and documentation
#414
mkorbel1
closed
1 year ago
0
Cleanup some doc and comments
#413
mkorbel1
closed
1 year ago
0
Fixes and improvements related to shifts
#412
mkorbel1
closed
1 year ago
0
LogicValue division with negative numbers doesn't work as expected
#411
mkorbel1
closed
1 year ago
1
Reset for flops and try ports
#410
mkorbel1
closed
1 year ago
0
`StateMachine` abstraction should expose mapping of identifiers to state index
#409
mkorbel1
closed
1 year ago
0
Optimize generation of SV for bus subset to eliminate extraneous assign statements
#408
mkorbel1
closed
11 months ago
0
Chapter 9 - Tutorials on ROHD Verification Framework
#407
quekyj
closed
1 year ago
2
Add multi-trigger (e.g. async reset) to abstractions
#406
mkorbel1
closed
1 year ago
0
Add `tryInput` and `tryOutput` that returns null if `input` and `output` don't exist
#405
mkorbel1
closed
1 year ago
0
Shifting large bit vectors (width > 64) can sometimes result in unexpected Dart exception.
#404
kimmeljo
closed
1 year ago
1
Unique case with multiple match behavior
#403
dmetis
closed
1 year ago
0
Lint cleanup
#402
mkorbel1
closed
1 year ago
0
The content of FSM in website user guide is confusing
#400
quekyj
closed
1 year ago
0
Add chapter 8 tutorials
#399
quekyj
closed
1 year ago
0
Fix blog link in README
#398
mkorbel1
closed
1 year ago
0
Fix some sensitive tests to be more robust
#397
mkorbel1
closed
1 year ago
0
Make "expected" message in SV testbench from SimCompare include width for invalid signals
#396
mkorbel1
opened
1 year ago
0
Sort ports in generated outputs
#395
mkorbel1
closed
1 year ago
0
Generate RTL for both classes even when two classes have identical contents
#394
sshankar4
closed
9 months ago
2
Gates should output X (never Z) when inputs are invalid
#393
dmetis
closed
1 year ago
2
Fix bugs where SSA could potentially generate inferred latches
#391
mkorbel1
closed
1 year ago
0
Fix bug where FSM may cause inferred latch
#390
mkorbel1
closed
1 year ago
0
Add branch coverage to script
#389
mkorbel1
closed
1 year ago
0
Refactor docs and README for website
#388
mkorbel1
closed
1 year ago
1
Fix bug with SSA reuse of signals
#387
mkorbel1
closed
1 year ago
2
Cases
#386
mjayasim9
closed
1 year ago
1
Add `previousValue` to `Logic`
#385
mkorbel1
closed
1 year ago
0
Wave dumping with `LogicArray`s and `LogicStructure`s
#384
mkorbel1
closed
11 months ago
3
Fix #382, if block exceptions when else is wrong
#383
mkorbel1
closed
1 year ago
0
An `If.block` with only one `Else` in it does not flag an error
#382
mkorbel1
closed
1 year ago
0
Issue#257: Added flop like function to construct FlipFlop
#381
Sanchit-kumar
closed
1 year ago
0
Chapter 7 bootcamp
#380
quekyj
closed
1 year ago
0
Add `PairInterface`
#379
mkorbel1
closed
1 year ago
0
Support a partial assignment `Conditional`
#378
mkorbel1
opened
1 year ago
0
Write part-assign automation for `LogicArray`s
#377
mkorbel1
closed
2 months ago
3
Complete testing for unpacked arrays in generated SystemVerilog
#376
mkorbel1
opened
1 year ago
0
`LogicStructure` and `LogicArray`
#375
mkorbel1
closed
1 year ago
0
Documents in `user_guide` aren't ideal for non-website viewing
#374
mkorbel1
closed
1 year ago
0
Issue#371 Made LogicValue Comparable
#373
Sanchit-kumar
closed
1 year ago
0
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