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Hello,
(I asked this in the mailing list, but I think it's better here as an issue, since I think it's a bug rather than some user error)
I recently updated one of our servers to 9.2, and curiou…
amisk updated
3 months ago
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Using the latest update on a waveshare with 32gb microsd.
I added some more snaps/tapes to the folders
snapshots - 748 items
tapes - 1296 items
hit 5 to refresh. It says scanning on-scr…
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Hi,
we've been observing some curious behaviour with the bulk staging service. It appears the bulk service does not trigger stages, if there are disk locations known to dCache, even when these pool…
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### Describe the bug
For megaboom v6, I upped the clock frequency to 833 MHz and the resulting clock tree appears to be unbalanced (see the branch of the tree on the far right in the viewer) and with…
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firrtl>> load ../riscv-mini/generated-src/Tile.fir
Total FIRRTL Compile Time: 374.3 ms
End of dependency graph
Circuit state created
Exception during evaluation: Expression key dcache._GEN_3 alre…
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Hi!
We are trying to confirm which verilog modules (such as ./bp_fe/src/v/bp_fe_bht.sv, ./bp_fe/src/v/bp_fe_controller.sv, ./bp_fe/src/v/bp_fe_pc_gen.sv, ./bp_be/src/v/bp_be_top.sv, ./bp_be/src/…
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### Description of Issue
I recently tried to get OpenUSD building for the Musl libc so that I could have a totally static build. To do this I'm using the nix flake I wrote for openusd: https://gith…
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**Type of issue**: bug report
**Impact**: new rtl
**Development Phase**: proposal
**Other information**
```
def onReset = L1Metadata(0.U, ClientMetadata.onReset)
val meta =…
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This branch contains updates in memfy and dcache to support concurrent read/write access if no address collision can occur. The updates are the following:
- memfy: `AXI_ORDERING` parameter set to 1…
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Hello,
I have successfully ported ThreadX and FileX on my own board STM32H735G DK and successfully run the Fx_uSD_File_Edit example.
But when I enable the FX_ENABLE_EXFAT macro and use the exfat for…