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First of all, thank you Lawrence for creating this great SD Card controller. It works like a charm for most cards (SD and SDHC).
There are two interessting effects on a SanDisk Ultra 32GB SDHC (Cla…
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The use case is to be able to control the core and menu without needing physical access to the MEGA65. This could either be done over the serial (UART) port or over Ethernet.
This feature can be im…
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Make all operating system functions that are working with hardware registers ISR-safe. For context, read https://github.com/sy2002/QNICE-FPGA/issues/109#issuecomment-693892892.
```
isr_mulu
isr_m…
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This test should verify that the CPU performs the correct read's and write's on the external bus. This is important when addressing I/O devices, and this issue is created as a result of this comment: …
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* We need to document these semantics somewhere (possible interrupt device documentation, best practice programming, ...)
* One new best practice is, to set the ISR to the own RTI before disabling an…
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This issue is part of #67 and issue #66.
We (Mirko and I) are thinking about breakpoint and single step support in QNICE and came up with the following idea:
* We will use one of the two spare bit…
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As a result of our video conference last Saturday: For solving everything related to future ISA changes in V1.7 and later (project "clean ISA", issues #57 and #55 etc.) and the related potentially lar…
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If one of the Math PhDs @bernd-ulmann and @MJoergen would like to do me a favor, then you could implement these `SHL32` and `SHR32` stubs in `monitor/math_library.asm` (and maybe even add a test progr…
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## Environment
```sh
Wed Dec 28 03:22:07 PM EST 2022
radare2 5.8.1 29769 @ linux-x86-64 git.5.7.8-780-g99b72288bf
commit: 99b72288bf01b736e69ea5271935ec8b1cc2d495 build: 2022-12-28__14:38:38
Li…
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One of the basic ideas of QNICE-FPGA is, that it is meant to be highly portable. For sure we are not there, yet ;-)
Currently, everything is quite Xilinx specific.
* Right now, we have two hardw…