New semantics of our interrupt devices

sy2002 / QNICE-FPGA

QNICE-FPGA is a 16-bit computer system for recreational programming built as a fully-fledged System-on-a-Chip in portable VHDL.

http://qnice-fpga.com

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New semantics of our interrupt devices #136

Open sy2002 opened 4 years ago

sy2002 commented 4 years ago

We need to document these semantics somewhere (possible interrupt device documentation, best practice programming, ...)
One new best practice is, to set the ISR to the own RTI before disabling an interrupt.
The timer will be disabled if any of the two registers prescaler or timer is zero.
The VGA scanline interrupt will be disabled, if bit 15 of the scanline register is set.
Test programs (timer test, fancy, ...) need to be adjusted
Emulator needs to be adjusted
sysdef.asm (and comments within sysdef.asm)?
Others?

sy2002 commented 4 years ago

We must not forget to adjust the assembler and C test programs to adhere to these new semantics and to our new ISR best practices. I adjusted test_programs/fancy.asm but all the others are still adhering to the old semantics.

sy2002 commented 4 years ago

We also must not forget to adjust all assembler and C test programs to activate interrupts at first because interrupts are now disabled by default (see https://github.com/sy2002/QNICE-FPGA/issues/139#issuecomment-694474689)

MJoergen commented 4 years ago

I suggest the Monitor enables global interrupt.

sy2002 commented 4 years ago

@MJoergen Can you take this one and finalize it? The remaining TODOs as far as I oversee them correctly are:

[x] Hardware: Adjust the VGA to the new semantics
[x] Hardware: Adjust the timer module to the new semantics and also adjust the comments in the two file's headers as they describe the old semantics
[ ] Make sure the Monitor enables the global interrupt
[x] Adjust fancy to the new semantics
[ ] Adjust all other interrupt test and demo programs in assembler and in C