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I'm not sure if I'm just looking in the wrong place, but I can't find anywhere where I can see the state of the RISC-V CPU registers of my Pi Pico 2 in the VS Code Debug panel. I can read them with th…
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### Posting because I cannot find mention anywhere
I have seen that mono supports the RISC-V architecture but cannot find anything relating to .NET 5 support for RISC-V.
Are there any plans to sup…
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Building on issues #1470 #1369 #1253 #1396 #1567 and aligning with the [RISC-V Unified Database](https://github.com/riscv-software-src/riscv-unified-db) efforts, I've made some tweaks that I believe c…
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Testcase:
```c
int a;
char b = 48;
long c[256];
int main() {
for (long d = 163 - 161; d < b - 33; d += 2)
a = ({
__typeof__(0) e = ({
__typeof__(0) f = ({ c[6]; });
…
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RISC-V is a new kind of CPU architecture that's free and open source, as well as pragmatically designed to be easy to learn yet powerful enough to be useful for real world projects. It's already well …
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# RISE RISC-V Developers Appreciation Pilot Program Submission Process
## In a comment under this issue please include:
* **Project Name and Description:** Provide a brief overview (1 to…
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### Resource Title
Teaching experiences with RVfpga
### Resource Description
In the GitHub repository [RVfpga-sim-addons](https://github.com/artecs-group/RVfpga-sim-addons), we demonstrate ho…
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### Describe the problem
I am evaluating the possibility of using Tauri to build desktop applications for the RISC-V platform. I would like to know if Tauri currently supports the RISC-V architecture…
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VSEARCH could be adapted to run on [RISC-V](https://en.wikipedia.org/wiki/RISC-V) systems. The SIMD code would need to be translated to the vector capabilities of this platform.
Until we have actua…
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More to follow