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Currently, it is not possible to
* model an accelerator in the SLAM MoA;
* specify multiple implementations (or refinement) for the same actor with the scheduler knowing the specific timings of a gi…
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I ran a benchmark that calculates a Fibonacci-style sequence which includes source code of the form:
c = a + b
d = a + b
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https://github.com/desul/desul/blob/fd6cd0639863a48ae0c57ed5db286955d6a412e2/atomics/include/desul/atomics/Lock_Array_SYCL.hpp#L97-L107
is used to enforce synchronization between work items and `re…
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Hello,
the bug appears on the tandem mode (solo mode we know this) on the minstret value in the CSR, the problem look like is rrelated to activated the Superscalar mode on the RTL side, so the instr…
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```
root@pve2:~# lspci -vv |grep -A18 -i sas
03:00.0 Serial Attached SCSI controller: Broadcom / LSI SAS2008 PCI-Express Fusion-MPT SAS-2 [Falcon] (rev 03)
Subsystem: Dell 6Gbps SAS HBA Ada…
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The current design of SG16 is strictly a single microprocessor core. The modular design of the emulator means that a front-end could easily run multiple instances in parallel, synchronous or not, but …
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The current RV32/64I EABI looks like being overoptimized for a specific single issue pipeline design (and instruction memory latency) by sacrificing the overall ABI performance in favour of achieving …
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This bug was initially reported in #708.
> Consider the following scenario while executing from nonidempotent memory:
>
> 1. A branch instruction is fetched => `speculative_d = 1'b1`
> 2. The i…
niwis updated
2 months ago
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| | |
| --- | --- |
| Bugzilla Link | [18605](https://llvm.org/bz18605) |
| Version | trunk |
| OS | Linux |
| Reporter | LLVM Bugzilla Contributor |
| CC | @atrick,@chandlerc,@echristo,@hfinkel |
…
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Hi,
I was looking at some Coremark performance number to compare against https://github.com/SpinalHDL/NaxRiscv, but got multiple issues :
- Can't find any documentation about coremark performanc…