-
It might be cool to synthesize some timing diagrams for subsets of LF programs that are driven purely by timers and/or based on execution traces. This idea was stimulated by [PlantUML](https://plantum…
-
## Reason
This is a standing issue to keep track of tests that commonly timeout on civet. The timing for these tests should be decreased where possible.
### Framework
- [ ] mortar/continuity-3d…
-
Server-Timing is a one-trick pony. It would be nice if was a header that could express any server metric rather than just times, which are interesting, but only part of the story if you're trying to a…
-
For battery driven devices, it makes sense that `set` topics are retained. So instead of reinventing the loop of checking availability and only sending if awake in the Homie controller, we can actuall…
-
This is to track some of the things that a new timing analysis engine in nextpnr needs:
- hold time analysis and satisfaction (by making routes longer/inserting feed-through LUTs)
- min/max dela…
-
The current lookahead in the FPGA interchange implementation is [disabled by default](https://github.com/YosysHQ/nextpnr/blob/692d7dc26ddf21e2d38dd16aecef652ab4c0d5e3/fpga_interchange/arch.cc#L49) bec…
-
In some designs (e.g. [ram-test](https://github.com/YosysHQ/nextpnr/tree/master/fpga_interchange/examples/tests/ram)), the clock net crosses a clock region and gets into the general interconnect.
!…
-
Currently VPR has no notion of falling edge clocks. All clocks are implicitly assumed to be rising edge so is clock edge sensitivity of flip-flops / latches. Static timing analysis does not support fa…
-
This should be done after some of the other wirings are first complete, but eventually we need a controller wiring that does the routing of an event to the wiring that it should take on. When we get h…
-
I've read the BLHeli_S firmware a few times and had some questions that I'm hoping you all can help with.
Questions about BLHeli_S with **A.asm**. I arbitrarily chose **A.asm**.
**A.asm:**
Hard…