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I have been trying to execute pio-block-sifive in its preonboarded state exactly as mentioned in the README tutorial [here][preonboarded] but have encountered some problems espeically when running the…
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Sadly almost nothing to include with the report, left the current April 19th Fedora image, kernel 5.10.6+ running overnight.
System apparently wandered off and just stopped responding, dropped netw…
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rm -rf obj/x86_64-linux-ubuntu14/build/riscv-gnu-toolchain/build-binutils-newlib/
mkdir -p obj/x86_64-linux-ubuntu14/build/riscv-gnu-toolchain/build-binutils-newlib/
cd obj/x86_64-linux-ubuntu14/bui…
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I have configured an SoC by using Rocket-Chip SoC generator but I am unable to find any parameter that can configure GPIO(General Purpose Input Output) for the SoC.
Is it automatically configured?
H…
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Hello,
I am facing issue building the sample demo applications for SiFive HiFive1 board.
I have mentioned this issue in the riscv-gnu-toolchain repository reference can be found [here](https://git…
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I only found bitbake-1.46.3 in https://github.com/openembedded/bitbake/tags.
```
luyahan@plct-build-4:~/riscv-sifive$ bash ./meta-sifive/setup.sh
Init OE
You had no conf/local.conf file. This con…
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Can you extract the same part to support other ISAs? Maybe make a new extension. It would be helpful!
mttbx updated
3 years ago
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CPU: E21
toolchain: riscv64-unknown-elf-gcc-8.3.0-2020.04.0-x86_64-linux-ubuntu14.tar.gz
when I run hello.c, modify the code as below:
**int main(){
unsigned long long val = 0x12345678…
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now, i have x86-ubuntu and riscv-toolchains , so i can build "helloworld" which can be run at riscv. And there are a machine which chip just support ISA rv64imafd (No Compress Instruction), so when i …
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I tried compiling the newlib compiler for almost all possible targets using multilib-generator format similar to that in sifive freedom tools and that works for all -march and -mabi combinations inclu…