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With Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition, `./build-bladerf.sh -r hosted -s 115` bombs out with:
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Error (10839): Verilog HDL error at nios_system.v(225): '1 is a Sy…
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When issue #65 was implemented I didn't realise it was permissible to overload standard system tasks in a custom VPI library. Conforming simulators _should_ call the user-defined task instead of the …
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Author Name: **Jonathon Donaldson**
Original Redmine Message: 1404 from https://www.veripool.org
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I have a simple video driver design written in SystemVerilog that I'm compiling with veri…
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Author Name: **Art. FR**
Original Redmine Message: 1331 from https://www.veripool.org
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All,
I would like to validate my verilated RTL code using my existing HDL testbench in a commercial…