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I'm running a test to compare the result of software remainder operation and pcpi_div hardware remainder operation. When the operation is 00000001 % 800ab000, the result is not same: 00000001 % 800a…
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```
The following builds failed!
=============================================
arty bridge_net lm32
arty bridge_net or1k
arty bridge_net picorv32
arty bridge_net vexriscv
arty ddr3 lm32
a…
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## Steps to reproduce the issue
Using [picorv32.zip](https://github.com/YosysHQ/yosys/files/3294223/picorv32.zip), run `yosys -p "synth; extract_fa" picorv32.v`.
Reproducible on a3a80b75 and lat…
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my c code:
```c
void entry(void)
{
extern unsigned int _bss;
extern unsigned int _ebss;
for (unsigned int *dst = &_bss; dst < &_ebss; dst++)
*dst = 0;
main();
}
```
…
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## Steps to reproduce the issue
```
./yosys -p "synth_xilinx -abc9" picorv32.v &> nodebug.out
./yosys -p "synth_xilinx -abc9" picorv32.v -g &> debug.out
diff debug.out nodebug.out -y
```
gives…
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At https://github.com/cliffordwolf/picorv32 (in `README.md`) I see:
> A PCPI core that implements the \`MUL[H[SU
I expected:
> A PCPI core that implements the \`MUL[H[SU **|U]]** \`
(the fragm…
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## Steps to reproduce the issue
./nextpnr/ice40/picorv32.sh
Using commit dd8d264b:
ICESTORM_LC: 1540/ 7680 20%
Info: Max frequency for clock 'clk_$glb_clk': 70.88 MHz (PASS at 12.00 …
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ice40 has a special carry structure that taps the input of a LUTs, rather than the output:
![image](https://user-images.githubusercontent.com/6740044/61389113-3116f300-a86d-11e9-8c09-2a31204740fc.png…
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According to https://github.com/cliffordwolf/picorv32/issues/92 picorv32 RISC soft core runs on Alhambra board. Is it possible to add support for this to FPGArduino?
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## Steps to reproduce the issue
`./yosys -p "proc; techmap; opt; dump" case1.v`
Minimised from https://github.com/cliffordwolf/picorv32/blob/e0baf2e0bd49fdddef2e3440c1f6364478655154/picorv32.v#L…