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# Add a Verilog / SystemVerilog support to [Sphinx](https://sphinx-doc.org)
# Brief explanation
We use [Sphinx](sphinx-doc.org) for documentation heavily. Sphinx currently doesn't support Verilo…
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This was submitted to the mailing list by Christopher K. Johnson. I'm just
adding it to the issue list since the decision was to have patches moved
here to keep things organized.
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In t…
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```
This was submitted to the mailing list by Christopher K. Johnson. I'm just
adding it to the issue list since the decision was to have patches moved
here to keep things organized.
-----------
In t…
-
```
This was submitted to the mailing list by Christopher K. Johnson. I'm just
adding it to the issue list since the decision was to have patches moved
here to keep things organized.
-----------
In t…
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In multiple source files, a conditional signal assignment statement is used within a process, which is illegal in VHDL-2008. Instead an if statement or case statement should be used.
During compila…
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If I do :
s=hs.load('zone 2.bcf', signal_type = "EDS_TEM")
I get the following warning:
"WARNING:hyperspy.io_plugins.bcf:spectrum have no dead time records..."
Then a number of parameters are …
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In order to use different applications with different purposes over one can-open instance or hardware- interface I am thinking about the best method to do or implement this.
Those applications could …
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Hi All,
You are my last chance, I spend days to resolve that.
I put this board into my old 3D( Malyan M180). I wired all the connections. However, I fail on Z Endstop. He don’t want to work.
The ot…
Esla2 updated
3 years ago
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Hello,
I know this has been discussed a bit, but just curious what the software side of the Wixel is doing with the xBridge2 27K/10K voltage divider, and what the levels are.
4.2V with a 27K/10K com…