-
**Environment**
VSG 1.6.1., Fedora
**Describe the bug**
The library_001 complains in a context environment (VHDL-2008) where the indentation is actually correct.
**To Reproduce**
Run VSG on t…
-
Hi all, I'm reposting this from https://github.com/prettier/plugin-php/issues/1537 since the plugin is not responsible for editor integration.
========================
**Summary: I want to use P…
-
There seems to be an issue with the `enable-latex: true` option.
Works fine with `enable-latex: false`.
Any idea what I am doing wrong?
```
name: CI/CD
on:
push:
branches:
…
KochC updated
3 years ago
-
### Summary
I'm attempting to pack a repository (https://github.com/PostHog/posthog) using pack. It seems to only pickup the Python buildpack. However, there is also a package.json, which should trig…
-
The circuit database has to be somehow implemented in every project related to HDL/FPGA etc.
This leads to ridiculous amount of work for developers of such a libraries and also makes this libraries i…
Nic30 updated
4 years ago
-
Hello,
I would like to use tests in your repository as a tests for [VHDL/SV parser platform](https://github.com/Nic30/hdlConvertor/tree/sv2017).
It is not easy to automatically determine if the …
Nic30 updated
4 years ago
-
Xilinx and some other vendors provide a file called `vhdl_analyze_order` per VHDL library, containing one source file per line. This file can be read by Tcl, Bash or what ever language to execute the …
-
In an attempt to use everywhere the same javacc version (I use 6.1.2, @doxygen uses an unofficial self generated 6.2) and simultaneously going to the latest javacc version (7.0.5), the switch was made…
-
Cppcheck 1.89 changes the warning output to match gcc better, but this breaks ALE's linter parser.
## Information
**VIM version**
NVIM v0.4.3
Build type: RelWithDebInfo
RHEL7
## Wh…
-
Hi @rodrigomelo9,
This type of project seems like it would be an excellent addition to the SymbiFlow project. Did you want to join forces here?
The rest of the SymbiFlow project is using the fol…