Nic30 hwt issues - Githubissues

Nic30 / hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

MIT License

194 stars 26 forks source link

issues

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Incorrect initialization with Verilog serializer

#46 jesseclin opened 3 months ago
3
Native Async reset support in RtlNetlist?

#45 jesseclin opened 3 months ago
4
Update signalOps.py

#44 jesseclin closed 3 months ago
1
Instantiate VHDL or Verilog IPs as black-boxes

#43 jesseclin opened 4 months ago
2
assigment semantics unclear

#42 philipaxer closed 1 year ago
2
add_param_asserts breaks examples

#41 philipaxer closed 1 year ago
5
Issues with basic example

#40 kiteloopdesign closed 2 years ago
3
Complete tests for assignments to a cast or slice of registers

#39 Nic30 closed 3 years ago
1
Tests for StructIntf._eq/__ne__ operators

#38 Nic30 closed 3 years ago
1
Tests for replace_input_in_expr

#37 Nic30 closed 3 years ago
1
Complete tests for RtlSignals generated from composed types like HStruct, HArray

#36 Nic30 closed 2 years ago
1
Add a Gitter chat badge to README.md

#35 gitter-badger closed 3 years ago
0
IP core importing

#34 Nic30 opened 4 years ago
3
Support for formal verification statements

#33 Nic30 closed 2 years ago
2
Convert interfaces to HDL as well (VHDL records, SV interface)

#32 Nic30 opened 4 years ago
0
Multiple component variants for specified parameter combinations under wrapper

#31 Nic30 closed 3 years ago
2
rm relicts of interface direction discoverry logic

#30 Nic30 closed 4 years ago
1
Proper tutorial - python project packaging and distribution, doc, visualization

#29 Nic30 opened 4 years ago
1
Prevent from dupliacation of generic/params if it shares same value

#28 Nic30 closed 4 years ago
1
Proper tutorial - simulations/verifications

#27 Nic30 opened 4 years ago
2
Proper tutorial - compilation phases and serialization customizations, vendor tools integration

#26 Nic30 opened 4 years ago
2
Proper tutorial - components, interfaces

#25 Nic30 opened 4 years ago
2
CLI utils for component/interface introspectivity

#24 Nic30 closed 4 years ago
1
Clean stack trace for exception in RtlSignal operators

#23 Nic30 closed 4 years ago
1
multidimensional index in vhdl

#22 Nic30 closed 4 years ago
1
Error with sensitivity lists in If statement

#21 benreynwar closed 4 years ago
2
Extract rtl simulator

#20 Nic30 closed 4 years ago
1
Extract bit precise math

#19 Nic30 closed 4 years ago
1
replace internal representation of hardware with netlistDB

#18 Nic30 closed 4 years ago
1
naming optimizations

#17 Nic30 opened 5 years ago
0
Extraction of netlist graph database and HDL parser/serializer modules

#16 Nic30 closed 4 years ago
4
Extract the simulator

#15 Nic30 closed 4 years ago
2
minor review of README

#14 mgielda closed 5 years ago
2
Help with design low-level HDL language

#13 XVilka closed 5 years ago
3
Interface direction in definition of component

#12 Nic30 closed 5 years ago
1
C/C++ library for IO access to HW in sim. (for driver development)

#11 Nic30 closed 5 years ago
4
Extract interface arrays

#10 Nic30 closed 5 years ago
1
readable debug of Value instances

#9 Nic30 closed 6 years ago
2
Condition tree rework

#8 Nic30 closed 6 years ago
1
Quartus ip core compatibility

#7 Nic30 closed 6 years ago
3
tests for operators with signed Bits

#6 Nic30 closed 7 years ago
1
Add a Gitter chat badge to README.md

#5 gitter-badger closed 7 years ago
0
If then else block can't find its block automaticaly

#4 Nic30 closed 8 years ago
1
Params are not working at hierarchical interfaces

#3 Nic30 closed 8 years ago
1
params are not set on component instances

#2 Nic30 closed 8 years ago
1
Value of param at top level is invalid

#1 Nic30 closed 8 years ago
0