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0. Could you send email to xianjun.jiao@ugent.be to introduce your self?
1. Our image is used directly or you build your own image?
2. What is your own modification?
3. Versions: OS, Vivado, …
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Hello,
I wanted to understand the design (IP and the project hierarchy) so I just wanted to load the design in vivado. I am getting the following error on 'source ./openwifi.tcl'.
```
# set_pro…
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Hi,
Following **Quick Start** instructions I can see openwifi AP on my phone and get connected successfully. However, after updating latest FPGA bitestream following **Update FPGA** instructions. My…
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Hi,
I am trying to retrieve RX timestamp metadata on ad9361 with libiio. However, it seems that lots of people have tried and failed on this. Are there any recent updates on this?
In the /examples…
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- Project to build: adrv9361z7035/ccbob_lvds with zynq device changed from z7035 to z7045 induatrial grade version for custom board but our board has ad9364 instead of ad9361.
- Petalinux version: …
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**Environment**
- Project to build: adrv9361-z7035
- Petalinux version:2019.1
- HDL branch: hdl_2019_r2
- META-ADI branch: 2019_R2
**Bug**
My custom hardware board is based on AES-PZSDR…
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``dma:` dma@7c420000 {
compatible = "adi,axi-dmac-1.00.a";
reg = ;
interrupts = ;
clocks = ;
#dma-cells = ;
adi,channels {
#size-cells = ;
#address-cells = ;
dma-channel@0 {
…
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Hi,
I would like to evaluate this project but since the target is the zc706 board with a zynq xc045 device a Vivado license is needed and it's not free.
I tried to modify the target to the ZC702 …
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hello:
I'm want to use "Update FPGA" function, but I'm following the quick start and meet the error shown as below when running ./fosdem.sh
root@analog:~/openwifi# hostapd -dd hostapd-openwifi.conf …
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Hi,
I am using srsLTE on the UE side and I use this driver and ADRV9361 board for that. In the early stages of the connection, after MIB decode, before finding the PLMN, I see these lines from srsL…