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How do you create wallet for this particular project
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I observed similar behaviour with other collectives, but thus far only reproduced it with broadcast, so the title may be misleading. I will add comments of similar behaviour with other collectives her…
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Hi.
I'm trying to run neptune example in alveo directory.
But in my environment, the example is not work.
I started server as typing "./run.sh" and I accessed :8998.
I was trying to start …
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Currently we do not own any of the supported platforms but we are interested in adding ESP to our workflow. We do have other FPGA boards we would like to use.
I was wondering how easy would it be t…
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In order to download fpga.bit to Alveo board, I opened fpga.prj and start HARDWARE MANAGER, but I found no cards on localhost as the figure below shows:
![image](https://user-images.githubusercontent…
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To make localization more smooth. I think we can considering use fpga-shell to serve as standard shim. This can ease the maintaining burden, and make new platform supports more easy.
So my roadmap …
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This issue concerns the branch to resolve issue 196: https://github.com/Xilinx/ACCL/tree/196-reduceallreduce-issues-on-cyt_rdma
Gather sometimes switches up the output of the first rank and the sec…
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Hi [vt-lib-support](https://github.com/vt-lib-support),
Linking it to this issue(https://github.com/Xilinx/Vitis_Libraries/issues/80) as the 2020.2 is also failing.
I have been working on gettin…
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Hi,
I run the xbutil scan flash after opening the mluser docker container and get the following result:
`mluser@xxx:/opt/xilinx/xrt/bin$ sudo ./xbutil flash scan
Card [0]
Card BDF: 0000:01:00.…
SRQ91 updated
5 years ago
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Hi.
I saw your interesting projects on the Innova2 - and wanted to ask you:
Have you used the Innova2 FPGA to control the network chip's (ConnectX-5) ingress/egress packets?
I want to hack some…