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Before
```
03:04:13 | cd /root/work/xc7/counter_test/build/zybo && symbiflow_write_bitstream -d zynq7 -f top.fasm -p xc7z010clg400-1 -b top.bit
03:04:13 | Writing bitstream ...
03:04:15 | /roo…
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![image](https://github.com/f4pga/prjxray/assets/64728767/8b1a527e-4000-4ec7-b779-96b8c324da93)
I am following the procedure to download prjxray.
I ran the command: make db-prepare-parts
It t…
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To add spartan7 into arch_def flow, I do some modification based on [this pr](https://github.com/SymbiFlow/f4pga-arch-defs/pull/2374/files) and ran the arch_defs flow completely. But how do i verify …
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Generating bitstream by following the steps mentioned in this Makefile: https://github.com/Talha-Ahmed-1/picofoxy/blob/main/fpga/Makefile
It got stuck at the time of synthesis and giving such error…
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Hi,
I copy-past the verilog code inside my fpga. For info i use one UM232H board (FT232H chip) connected with one Digilent CMOD Board (fpga xilinx artix7). 8bits and 16bits transfer working very well…
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Hi, I'm following the doc on https://symbiflow-examples.readthedocs.io/en/latest/building-examples.html and the first 2 examples work fine, but litetx is not as clear.
First "Linux LiteX demo" does…
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The following error shows up from time to time on the Vendor tools CI, regarding the baselitex test:
```
FAILED: cd /tmpfs/src/github/symbiflow-arch-defs-presubmit-xc7-vendor/build/xc/xc7/tests/so…
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The CI fails to build `nexpnr-xilinx`: https://github.com/hdl/conda-eda/runs/5446064939?check_suite_focus=true#step:4:1613
```
+ pypy3 xilinx/python/bbaexport.py --device xc7a35tcsg324-1 --bba /ho…
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#### Proposed Behaviour
Placer should be place instances to take advantage of dedicated routing resources
#### Current Behaviour
Placer only uses delay matrix to choose placement decisions
…