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Hello,
I've build the Ibex safe version for the Arty A7 100T board at 33MHz.
I've a correct result on /dev/ttyUSB1:
```
Ready to load firmware, hold BTN0 to ignore UART input.
```
I've build…
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## Observed Behavior
When I try to simulate the Arty A7-35 example in Vivado, I get an error message in elaborate.log:
ERROR: [XSIM 43-3409] Failed to compile generated C file xsim.dir/top_art…
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Hi,
I am unable to extract mcs file, while extracting it is showing "xc7vx485tffg1761-2"part is missing even though Iam using the vivado version 2016.4. Please help me in solving this issue.
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I have set up the UART example with Arty A7 100 board and I observe the following:
When I send data to the USB descriptior as:
```
echo "AAAA" > /dev/ttyUSB3
```
In the minicom I can see
…
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https://reference.digilentinc.com/reference/programmable-logic/arty-a7/arty_a7_100_risc_v/start
I am trying to implement the above link to learn about RISC-V. However when I try ./build.sh I get a …
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Currently there is some half-implemented chaosnet code in `xbus_chaos.v`, but even if the code was finished there needs to be a physical layer in order for it to actually work. Since the Arty A7 has …
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So I am using WSL2 in Windows to have an Ubuntu install without having to deal with dual booting. This has posed certian challenges, such as getting USB devices (an Arty A7 board for example) passed t…
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Hi all,
I am interested in implementing the rocket core(s) on either the Arty35T or the Arty100T.
However, I would like the core(s) to have access to the 256MB of off-chip memory available on thes…
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I designed my own CFU to accelate FFT.
However, after `make prog` step was finished successfully, my terminal got stuck somewhere in `make load`.
```
make[3]: Leaving directory '/home/limx/CFU-Play…
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I am trying to build FemtoRV petitbateu but it fails to build two different ways for two different toolchains.
When I build with yosys+nextpnr using command: `python3 -m litex_boards.targets.digile…