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I want to make a net of a top-level input port become a clock source so that I can constrain it using SDC directive(s).
The target FPGA architecture requires that there is a `CLOCK_CELL` IO buffer …
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My laptop has 10GB available according to /proc/meminfo. I see this error running the `counter_test` example with `TARGET=nexys_video`:
```
Serial number (magic cookie) for the routing is: 416094…
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This version of Yosys needs updated to work with `nextpnr-xilinx`.
Running the `attosoc` example with this version of Yosys results in:
```
+ ../../../nextpnr-xilinx --chipdb ../../xc7a35t.bin …
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Since BLIF file cannot handle inout ports, these are represented as a single net connected to both input and output port with the same name. This creates an issue when something drives that net as the…
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When I attempt to build the PicoSoC demo by running `TARGET="arty_100" make -C picosoc_demo`
it initially appears to build the example but then I get his error:
`Successfully finished Verilog fr…
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#### Expected Behaviour
Given that ``check_route`` should just be a sanity check, I would expect it to be a fast check.
#### Current Behaviour
Currently ``check_route`` appears to take a lo…
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Here is the branch with the current progress on OpenTitan support:
https://github.com/antmicro/symbiflow-arch-defs/tree/opentitan_earlgray
Currently, I'm struggling with the error in `vpr_io_place…
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![screenshot from 2018-05-03 21-07-12](https://user-images.githubusercontent.com/18452276/39612703-7f58e1ba-4f16-11e8-9e7b-3db61fccbb95.png)
The above routing fabric has the indicated CHANX def…
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VTR fails with the following message when running the code below:
```
Error 1:
Type: Blif file
File: top.eblif
Line: 204
Message: Failed to find matching architecture model for 'ISERDESE2'
`…
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We currently use the --symbiflow flag to generate the minilitex design.
This was related to the fact that the PLL generate extra clocks and BUFG which are not used, ending up in clocks generated in t…