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ARTIFACTS (.v) files not being generated after running after invoking the command- "rtl -a /demo/arch/pynqz1.tarch -s true" the RTL Summary is generated but not the .v files
OS- Windows 10
Errors:…
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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard)
- [X] Yes, I searched [prior issues](https://github.com/ucb-bar/chipyard/issues)
- [X] Y…
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Patmos emulator fails to build when the method cache is replaced by a direct-mapped instruction cache in `hardware/config/default.xml`:
```
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+
```
Several exceptions are raised during the …
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So far, there has been a sequence of three successive workaround/fixes that have gradually moved closer to ideal FIRRTL dedup performance.
1. Turn off dedup entirely with a global `firrtl.transform…
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Hi Tom,
Thanks a lot for starting the model checking support and now this library effort.
Just wanted to let you know that I recently wrote a SMT backend for firrtl which made it into the `1.4` …
ekiwi updated
3 years ago
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```scala
// See LICENSE.txt for license details.
package solutions
import chisel3._
// Problem:
//
// 'out' should be the sum of 'in0' and 'in1'
// Adder width should be parametrized
//
c…
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This is a tracking issue for an effort to switch Calyx's testbenching.
## Background
Currently, all Calyx-compiled Verilog programs use the same [standalone testbench](https://github.com/calyxir/…
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The FullAsynchronousResetTransform no longer removes its annotation, which can lead to problems where the pass is no longer idempotent. It seems like some work has gone in to minimizing the amount of …
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using firtool-1.75.0 from github releases
I expect firtool to be able to lower enum types [as specified in the ABI](https://github.com/chipsalliance/firrtl-spec/blob/e53da0ca1b55d002e3c2c640b8a170b…
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Hello, I am very sorry to bother you. I have seen your paper "Chiffre: A Configurable Hardware Fault Injection Framework for RISC-V Systems " and I’m very interested in your Chiffre Fault Injection F…