calyxir calyx issues - Githubissues

calyxir / calyx

Intermediate Language (IL) for Hardware Accelerator Generators

https://calyxir.org

MIT License

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Add a `StaticSchedule` Analysis

#2033 calebmkim closed 2 days ago
1
place compile-invoke after static-promotion

#2032 paili0628 closed 2 days ago
4
changes on pass and primitives

#2031 paili0628 closed 2 days ago
0
Add bypass register primitive

#2030 matth2k opened 1 week ago
3
Update docs to note `fud` dependency on `calyx-py`

#2029 calebmkim closed 6 days ago
1
Queues: FIFO with length as a power of 2

#2028 anshumanmohan opened 1 week ago
0
Queues: Tidy the FIFO and PIFO

#2027 anshumanmohan closed 2 days ago
2
Docs: Document the three kinds of queues

#2026 anshumanmohan closed 2 days ago
0
Only trigger push event on main

#2025 rachitnigam opened 1 week ago
0
Generate or-and trees for guarded assignments

#2024 rachitnigam opened 1 week ago
3
Remove `@externalized` attribute and update `@data` documentation

#2023 calebmkim closed 1 week ago
1
Metadata

#2022 eliascxstro opened 1 week ago
0
`cell-share` Needs a Timing-Based Heuristic or Cost Model

#2021 andrewb1999 opened 1 week ago
1
Separate Out FSM in IR when during TDCC and `compile-static`

#2020 calebmkim opened 1 week ago
10
`@data` carried over to external memories

#2019 calebmkim closed 1 week ago
8
Probably fix #2016: Sort ports when compiling refs

#2018 sampsyo closed 1 week ago
2
eDSL: reserved names, nonexistent ports

#2017 anshumanmohan opened 1 week ago
2
Nondeterminism in wire initialization when using `ref` cells.

#2016 nathanielnrn closed 1 week ago
0
Allowing `invokes` to pass in subtypes to `ref` cells

#2015 nathanielnrn opened 1 week ago
1
[Profiling] Tracker Issue for Profiling first steps

#2014 ayakayorihiro opened 1 week ago
2
Mark `pipelined_mult` inputs as `@data`

#2013 andrewb1999 closed 1 week ago
1
`@data` default assignment optimization does not work on external memories

#2012 andrewb1999 closed 1 week ago
3
Do a Better Job At Removing Default Zero Assignments

#2011 andrewb1999 opened 1 week ago
0
eDSL: Make register names optional

#2010 anshumanmohan closed 2 days ago
4
Another change to pipelined_mult to improve QoR

#2009 andrewb1999 closed 1 week ago
0
Docs: Document dummy group delay trick for `static par` coordination

#2008 anshumanmohan closed 2 weeks ago
0
Fix typo.

#2007 cgyurgyik closed 1 week ago
1
Fix pipelined_mult frequency for Vivado

#2006 andrewb1999 closed 2 weeks ago
3
Updating DataGen Docs

#2005 calebmkim closed 2 weeks ago
0
Update Runt version.

#2004 cgyurgyik closed 2 weeks ago
1
Add an IR for BTOR2 to reduce the dependencies on the C parser

#2003 obhalerao opened 3 weeks ago
0
eDSL: new example, new docs

#2002 anshumanmohan opened 3 weeks ago
0
eDSL: Infer more widths, require fewer cell names

#2001 anshumanmohan closed 3 weeks ago
0
Actually parallelize reduction trees

#2000 anshumanmohan closed 3 weeks ago
1
Queues: Rethinking our PIFO

#1999 anshumanmohan opened 3 weeks ago
1
Eventually remove `tests/xilinx/cocotb` directory

#1998 nathanielnrn opened 3 weeks ago
0
Introduce verilog -> cocotb simulation `fud2` path

#1997 nathanielnrn opened 3 weeks ago
0
Remove `yxi` backend from `core` tests

#1996 nathanielnrn closed 3 weeks ago
0
Docs: version number and writing tweaks in page about `static`

#1995 anshumanmohan closed 1 month ago
0
Introduce calyx -> axi-wrapped-calyx `fud2` path

#1994 nathanielnrn closed 1 week ago
0
Toplevel `ref` cells are not kept after `compile_invoke` pass

#1993 nathanielnrn opened 1 month ago
0
Add a combinational constant multiplication primitive

#1992 andrewb1999 closed 1 month ago
0
Add combinational multiplier primitive

#1991 andrewb1999 closed 1 month ago
2
Parse error for large constants

#1989 Mark1626 opened 1 month ago
2
[Cider 2] Memory data dump format & serialization/deserialization

#1988 EclecticGriffin closed 1 month ago
0
Data conversion part 2

#1987 Angelica-Schell closed 1 week ago
0
Cider dap rework

#1986 eliascxstro closed 2 weeks ago
1
Use External Libraries To Generate A Single Verilog File

#1985 jiahanxie353 opened 1 month ago
0
Tests are being duplicated

#1984 rachitnigam closed 1 month ago
1
Revert "Add infrastructure for integrating BTOR2 interpreter into Calyx"

#1983 obhalerao closed 1 month ago
1