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calyxir
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calyx
Intermediate Language (IL) for Hardware Accelerator Generators
https://calyxir.org
MIT License
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Reimplement `static-timing` pass.
#909
mikeurbach
closed
2 years ago
57
Simulation Verilog
#1470
zzy666666zzy
closed
11 months ago
37
Calyx wrapper for Berkeley HardFloat Verilog library
#1928
jiahanxie353
opened
2 months ago
33
Zero-cycle transitions from dynamic to static control
#1828
rachitnigam
opened
4 months ago
30
(WIP) Cooley-Tukey NTT
#308
cgyurgyik
closed
3 years ago
28
Repeated output when looping and using the same primitive.
#284
cgyurgyik
closed
3 years ago
28
Relay: Support tensors
#184
sampsyo
closed
3 years ago
27
Fxdpoint dat
#292
yoonachang
closed
3 years ago
22
run specific passes from command line
#110
ViviYe
closed
4 years ago
22
Issues with Converting Onnx models to Calyx Code
#1157
calebmkim
closed
1 year ago
21
Determining the static interface for `calyx` components
#1725
paili0628
closed
5 months ago
20
Experience report: dry running the tutorial
#1508
anshumanmohan
closed
12 months ago
19
Separate Out FSM in IR when during TDCC and `compile-static`
#2020
calebmkim
opened
3 weeks ago
18
Single Port Memories
#1610
andrewb1999
closed
2 months ago
18
Tutorial: instructions for installation prior to the day
#1551
anshumanmohan
closed
10 months ago
18
Documentation for Python eDSL
#1413
rachitnigam
closed
11 months ago
17
Getting real VHLS comparison numbers
#162
rachitnigam
closed
3 years ago
17
Turn dynamic to static
#1419
paili0628
closed
1 year ago
16
[library] Use reset in `sqrt` to represent running state.
#753
cgyurgyik
closed
2 years ago
16
Error for comparions that are always true/false
#454
yn224
closed
4 months ago
16
[NTT] Explore faster NTT implementations.
#302
cgyurgyik
closed
3 years ago
16
improve `comb_prop`
#1931
paili0628
closed
2 months ago
15
Tutorial: toy arbitration logic
#1474
anshumanmohan
closed
12 months ago
15
Verilog backend overflows on large programs
#1273
susan-garry
closed
1 year ago
15
Add combinational components
#1203
andrewb1999
closed
1 year ago
15
Update to Dahlia means we Change some of the .expect files
#1187
calebmkim
closed
1 year ago
15
Simulating SCF designs
#759
rachitnigam
closed
2 years ago
15
Formatting for interpreter output
#733
EclecticGriffin
closed
2 years ago
15
Expand Relay frontend
#1154
calebmkim
closed
1 year ago
14
Axi test harness
#1153
nathanielnrn
closed
1 year ago
14
Failing continuous assignment simulation
#574
yn224
closed
2 years ago
14
Add fud stage to convert MrXL-native input to Calyx-native input
#1475
susan-garry
closed
1 year ago
13
`static-inline` generates incorrect guards
#1442
rachitnigam
closed
1 year ago
13
start merge-static-par pass
#959
paili0628
closed
2 years ago
13
Fixed point `std_exp`
#404
cgyurgyik
closed
3 years ago
13
fud2 Tracker
#1878
sampsyo
opened
3 months ago
12
Inliner revamp
#1813
rachitnigam
opened
5 months ago
12
rethink about the static interface
#1754
paili0628
closed
5 months ago
12
Unexpected calyx.std_extsi in fixed-point multiplication
#1738
zzy666666zzy
closed
7 months ago
12
PIFO Trees: Telemetry
#1736
anshumanmohan
closed
6 months ago
12
Documentation: need documetation in how to use how to generate Verilog from CIRCT generated Calyx
#1587
ManelMCCS
closed
10 months ago
12
Other bug is that in the `Toplevel` module, the port of instantiated hardware is different:
#1575
zzy666666zzy
closed
10 months ago
12
Deprecate `static` attribute
#1429
rachitnigam
closed
3 months ago
12
[calyx-py] Translate `gen_exp.py` to use the new builder
#1420
EclecticGriffin
closed
1 year ago
12
Reset ports for `seq-mem` are ignored in `reset-insertion`
#1354
calebmkim
closed
1 year ago
12
Proposal: Let Verilator generate its own `main` function
#1335
sampsyo
closed
1 year ago
12
Sync dot product
#1185
paili0628
closed
1 year ago
12
Resource estimator is producing segfault
#1174
susan-garry
closed
1 year ago
12
Add more memory primitives
#1038
andrewb1999
closed
1 year ago
12
[xilinx] Variable AXI requirement support
#888
yn224
closed
2 years ago
12
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