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calyxir
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calyx
Intermediate Language (IL) for Hardware Accelerator Generators
https://calyxir.org
MIT License
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[Profiling] Modifications to TDCC and scripts for first pass profiling
#2040
ayakayorihiro
opened
5 days ago
0
Add `CONTRIBUTING.md`
#1981
rachitnigam
opened
1 month ago
3
Separate Out FSM in IR when during TDCC and `compile-static`
#2020
calebmkim
opened
3 weeks ago
18
`@one_hot` attribute
#2042
calebmkim
opened
3 days ago
0
Metadata
#2022
eliascxstro
closed
2 days ago
0
New metadata format
#1979
eliascxstro
closed
2 days ago
2
[Cider 2] Connect to fud2 and the existing test suites
#2044
EclecticGriffin
opened
2 days ago
0
Cider 2.0 Tracker Issue
#1913
EclecticGriffin
opened
3 months ago
3
[Cider 2] Barebones Par
#2043
EclecticGriffin
closed
2 days ago
0
`gen_msb`: Tidying using modern eDSL
#2039
anshumanmohan
closed
2 days ago
0
Systolic, NTT: use more helpers for cleaner eDSL code
#1673
anshumanmohan
closed
2 days ago
9
eDSL: no `cells` list when defining new component
#2038
anshumanmohan
closed
3 days ago
3
[Cider 2] Memory loading & dumps
#2041
EclecticGriffin
closed
4 days ago
0
[Cider 2] Handle memory input/output
#1968
EclecticGriffin
closed
4 days ago
4
[Profiling] Tracker Issue for Profiling first steps
#2014
ayakayorihiro
opened
3 weeks ago
4
fud2 Tracker
#1878
sampsyo
opened
3 months ago
12
NTT: using a few "modern" eDSL features
#2034
anshumanmohan
closed
5 days ago
0
Support `new_fsm` attribute for tdst pass
#1363
calebmkim
closed
5 days ago
8
Add One-Hot Encoding for Static FSMs
#2037
calebmkim
closed
5 days ago
2
Calyx wrapper for Berkeley HardFloat Verilog library
#1928
jiahanxie353
opened
2 months ago
33
Systolic: modern eDSL features
#2036
anshumanmohan
closed
1 week ago
0
eDSL: Fix method names
#2035
anshumanmohan
closed
1 week ago
0
Queues: queues with lengths as powers of 2
#2028
anshumanmohan
closed
1 week ago
1
[fud] Process paths with spaces correctly
#1549
EclecticGriffin
opened
11 months ago
7
[semantics] Semantics of `Empty` vs `Seq`/`Par(Empty)`
#1526
EclecticGriffin
closed
1 week ago
9
Data conversion
#1977
Angelica-Schell
closed
1 week ago
2
`ir::Builder::add_group()` should take a done condition
#1119
calebmkim
opened
1 year ago
1
[Compiler] Move responsibility for opening files outside `Backend` traits `emit` fn
#1371
EclecticGriffin
closed
1 week ago
1
Expand keyword checks
#1361
EclecticGriffin
opened
1 year ago
3
Allow non-decimal values in parameters (e.g. `std_const`)
#1362
EclecticGriffin
closed
1 week ago
2
eDSL: new example, new docs
#2002
anshumanmohan
closed
1 week ago
0
Docs: refresh the page about the eDSL
#1908
anshumanmohan
closed
1 week ago
5
[Fud] Rename `SourceType.Terminal` to something less confusing
#1730
EclecticGriffin
closed
1 week ago
1
[Cider] Debug adapter tracker
#1746
EclecticGriffin
closed
1 week ago
1
Queues: Rethinking our PIFO
#1999
anshumanmohan
opened
1 month ago
1
[Calyx-FIRRTL] Script for generating FIRRTL primitives
#1863
ayakayorihiro
closed
3 months ago
1
Transient Conflicts in Interpretation Loop
#962
EclecticGriffin
closed
1 week ago
1
[library] Remove blocking statements.
#754
cgyurgyik
opened
2 years ago
2
Docs: further documentation of `static` features
#1885
anshumanmohan
opened
3 months ago
0
Queues: generalize PIFOs
#1810
anshumanmohan
opened
5 months ago
2
Hoist redundant parallel actions
#1661
anshumanmohan
opened
9 months ago
2
eDSL: `static_if_with`
#1785
anshumanmohan
opened
6 months ago
2
Create an AXI-interface generator implemented Calyx
#1733
nathanielnrn
opened
7 months ago
11
Add a `StaticSchedule` Analysis
#2033
calebmkim
closed
2 weeks ago
1
eDSL: Make register names optional
#2010
anshumanmohan
closed
2 weeks ago
4
changes on pass and primitives
#2031
paili0628
closed
2 weeks ago
0
place compile-invoke after static-promotion
#2032
paili0628
closed
2 weeks ago
4
Queues: Tidy the FIFO and PIFO
#2027
anshumanmohan
closed
2 weeks ago
2
Docs: Document the three kinds of queues
#2026
anshumanmohan
closed
2 weeks ago
0
FIFO, PIFO, PIFOTree: document the interface
#1660
anshumanmohan
closed
2 weeks ago
0
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