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### Link to Internship Posting
https://globalfoundries.wd1.myworkdayjobs.com/en-US/External/job/USA---Texas---Austin/Software-Engineering-Intern--Design-Enablement--Summer-2025-_JR-2403210
### Compa…
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DRC violations in GF018_5VGreen_SRAM_1P_256x8M8WM1 vs. documented rule in the design manual
## PL.12
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@antonblanchard just released the vlsiffra project. See the tweet @ https://twitter.com/antonblanchard/status/1580154261962657792
> Introducing https://github.com/antonblanchard/vlsiffra/ - a gene…
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## Expected Behavior
No Via resistance in tech lef
## Actual Behavior
Via resistance in tech lef
## Steps to Reproduce the Problem
1.
1.
1.
## Specifications
- Version:
- Platform:
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Is this repo the right place for the DRC and LVS rules?
I find it hard to discover and feels more general than closely tied to the "primitive cells".
/cc @mithro @QuantamHD
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Following Kwantae Kim's step-by-step introductions, everything is set up fine. However, changing the PDK in .bashrc is only explained for Skywater and GlobalFoundries. How do I set the variables prope…
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Deep mode DRC produces false positives on GF180MCU DRC CO.6a rule in latest KLayout. I'm attaching an archive with a minimized GDS from my Open MPW project where error manifests itself and a DRC scrip…
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This might be the case for other SRAM macros. 5.0V timing parameters should be used instead as Caravel runs @ a single 5.0v supply.
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https://github.com/google/globalfoundries-pdk-libs-gf180mcu_fd_pr/actions/runs/3904358547/jobs/6670037402
```
Warning: The `set-output` command is deprecated and will be disabled soon. Please upgrad…
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The transistors with a `.subckt` wrapper have `dtemp` on the `.subckt` line but `dtemp` isn't passed to the model instance so it does nothing. For example: https://github.com/google/globalfoundries-p…