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### Description
Unified Order allows you control your illusions/heroes via issuing a command whilst holding CTRL. The hifive and flag was added as part of battle pass and usually was removed afterw…
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Follow-up form https://github.com/seL4/seL4/pull/461
Look into L2 cache maintenance on RISC-V. So far nothing is implemented and for single core usage nothing seems to be needed.
These RISC-V p…
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hifive ver.1.2で追加されたAPIが候補に出るように定義ファイルを更新する。
simdy updated
8 years ago
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Can use https://github.com/HewlettPackard/osfci.
Need to figure out:
- What device to run CI on
- How to flash FW to SUT
- How to reset SUT
- How to collect serial log from SUT
Possibly fo…
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### Description
I would like to use [buildroot](https://github.com/buildroot/buildroot) to build linux kernel + rootfs and use it for renode board.
### Usage example
```
I followed some hints …
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**Describe the bug**
A clear and concise description of what the bug is.
**To Reproduce**
Steps to reproduce the behavior:
1. Build with options `riscv64.native.release`
2. Run test/program ' o…
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## Desired Feature ##
Enable RISCV64 CPU architecture support in order to build coreos-assembler for native RISC-V boards.
## PR ##
* https://github.com/coreos/coreos-assembler/pull/3459
## …
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Original Issue: apache/pulsar#13067
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**Is your feature request related to a problem? Please describe.**
Supporting Apache Pulsar on https://www.sifive.com/boards/hifive-unleashed
**Describe …
sijie updated
2 years ago
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It seems that only flash and ram is supported for reading in debug-mode. It would be great if memory on-chip peripherals (e.g. gpio) could be viewed, too. Currently, reading these leads to the followi…
U2654 updated
3 years ago
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Currently, we give the OS access to all of memory, and then blacklist regions (ex: where the sm lives).
We should reduce its default access to the smallest amount we can, likely 0x8000_0000 and hig…