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I am trying to import several modules including vart, xir, and vitis_ai_library in python script, while vart and xir are imported successfully, I could not import vitis_ai_library. I have searched thr…
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**Platform:** Avnet UltraZed EV Carrier Card
**Hardware Build:** Following this [design tutorials](https://xilinx.github.io/Embedded-Design-Tutorials/docs/2020.2/build/html/docs/Design_Tutorials/MPSo…
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Hi ikwzm,
This is a great project thank you - I am considering using it on our MPSoC project which is based on U96v2.
Quick questions:
1. I assume the boot image HW is the same as the base U96V…
aawce updated
3 years ago
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https://coldnew.github.io/b728d8e8/
在 UltraZed-EG PCIe Carrier Card 開發紀錄 系列文中，筆者曾經撰寫一些關於 Xilinx UltraScale+ MPSoC 系列的 Zynq UltraScale+ EG 這顆同時具有 ARM Cortex-A53、ARM Cortex-R5 以及 Xilinx FPGA 的 SOC。 …
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Added VitisAI 2.5 as user package like described in the manual.
While building VitisAI this output is shown:
```
WARNING: unilog-2.5-r0 do_fetch: Failed to fetch URL git://gitenterprise.xilin…
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Is it possible to run Vitis-AI 3.5 (and so, yolov7 and yolov8) on the KV260 target?
In [board_setup folder](https://github.com/Xilinx/Vitis-AI/tree/master/board_setup), there is only v70 and vek280…
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I am trying to run the desing on ZCU104
The image for the SD card is taken for here:
https://www.xilinx.com/member/forms/download/design-license-xef.html?filename=xilinx-zcu104-dpu-v2022.2-v3.0.0.im…
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Dear all,
I want to ask if it is possible to run it on the 3rd party board with the same zynq ultrascale+ fpga core.
due to my limited experience, i need to generate the wrapper file with the zynq p…
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Hello, I'm trying to port the Mars board example dma design to the ZCU106. Could someone explain the purpose of the system_top_PM3 file to me please? I see it in the template block design also but the…
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I followed the recently added ADI kernel build instructions and tried to boot from the SD card, but could not boot properly due to a kernel panic. It seemed that the root file system was not mounted p…