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does Shared memory allocation work on Intel N6001 board? i am able to run board_test
https://github.com/oneapi-src/oneAPI-samples/tree/master/DirectProgramming/C%2B%2BSYCL_FPGA/ReferenceDesigns/boar…
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| | |
|--------------------|----|
| Bugzilla Link | [PR49874](https://bugs.llvm.org/show_bug.cgi?id=49874) |
| Status | NEW |
| Importance | P normal |
|…
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### Describe the bug
https://github.com/intel/llvm/actions/runs/8628394148/job/23650791247?pr=13335#logs
```
******************** TEST 'SYCL :: USM/queue_copy.cpp' FAILED ********************
Exit…
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Est-ce que tu penses qu'il serait possible de développer un outil qui va scanner le fichier USM (donc la bande vidéo et les pistes audio) et remplacer l'une des pistes audios par une autre de notre ch…
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Hi, following conversations with @jbrodman and @Pennycook I am leaving this issue here as a placeholder. Currently the SubGroupNDRange Load and Save functions use sycl::multi_ptr
It would be good if …
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How do you get the keys of cutscenes?
And where is the keys of the following cutscenes?
```
CS_ChapLoop_Black.usm
CS_ChapLoop01_Act0010.usm
CS_ChapLoop01_Act0020.usm
CS_ChapLoop01_Act0030.usm
C…
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Refer to the https://github.com/intel/llvm/pull/11414 for the list of disabled tests.
Preliminary CI runs that drove selection of such tests:
https://github.com/intel/llvm/actions/runs/6411226892/…
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This is a custom site builder (similar to MyPortfolio and Carrd) that is primarily used for portfolio sites. Link formatting seems to somewhat uniform despite the many different formatting options, as…
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I was testing the Snmpv3 traps and found that the USM time synchronization is failing.
Reload the switch, upon booting the SLX will send the traps to the ubuntu server and from the packet capture w…
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the repo currently as a const.py module that contains errors. but the r'^user/register$', r'^user/login$',r'^user/sendregisteremail$', and r'^user/login$', all give the same response 200 in most scena…