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driver.cpp includes Vtop.h, which assumes the toplevel module is named top. circt-rtl-sim.py takes a parameter to set the toplevel name to something else, but the driver still assumes it's "top".
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Hi there!
In some hard-to-reproduce cases, some malloc assertion fails.
```
Vtop: malloc.c:2379: sysmalloc: Assertion `(old_top == initial_top (av) && old_size == 0) || ((unsigned long) (old_si…
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I get this error every time I try to run VTOP and I'm unsure of how to fix it.
I'm running Ubuntu 18.04.
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Hi,
When I install `vtop` while not being in a root shell, I get the following error:
```
/usr/local/bin/vtop -> /usr/local/lib/node_modules/vtop/bin/vtop.js
> husky@0.11.9 install /usr/loca…
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Empty console on start. Exits normally on mouse click or any key press.
Just installed from packages.
```
❯ pkg info gotop
gotop-4.1.3_1
Name : gotop
Version : 4.1.3_1
Instal…
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Hi,
I‘m using the release version of verilator-4.202 and here is my example:
```verilog
module top(clk);
input clk;
logic [15:0] index;
logic [15:0] data;
logic [15:0] mem[7:0];
alw…
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## Bug Description
An example:
`main.cpp`:
```c++
#include "VTop.h"
#include "verilated.h"
int main() {
VerilatedContext* contextp = new VerilatedContext;
VTop* top = new VT…
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On Windows, while using the MinTTY executable packaged with MSYS2, vtop crashes saying "Not a terminal".
I'm unable to use the default Windows commandline, as it doesn't support the unicode characters…
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The following generated verilog has two bugs in generation:
1) VTop does not have a clk signal (line 568 of uncorrected)
2) Invalid verilog syntax (line 48 of uncorrected)
[uncorrected is "assig…
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@toddstrader it seems that WAVES=1 and COMPILE_ARGS += --trace no longer produces a dump.vcd when using SIM=verilator
62f1839525e56ee6fe17f558d49aa513fbc7e745 it works
f7b37ca50ccd72ba99a608f5d…