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您好,SDK main.cc代码
unsigned int WEIGHT_BASE = 0x10000000;
unsigned int BETA_BASE = 0x1EC38000;
unsigned int MEM_BASE = 0x1EC53000;
我知道这是zedboard的保留内存。
我当前的主板是zcu104。
更改为zcu104可以指…
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It is my understanding that Antmicro want to support the ZCU10[45] dev boards.
* [ZCU104](https://www.xilinx.com/products/boards-and-kits/zcu104.html) - Zynq UltraScale+ XCZU7EV-2FFVC1156 MPSoC
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Hello, I follow the tutorials (https://github.com/Xilinx/Vitis-Tutorials/tree/2021.2/Vitis_Platform_Creation/Introduction/02-Edge-AI-ZCU104) and change board information from ZCU104 to ZCU106 in step1…
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Hello everyone,
I followed steps which is example of vitis-ai for zcu104, however all steps passed until putting the sdcard to the board.
In **version 2020.2** https://github.com/Xilinx/Vitis-Tu…
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Dear TAPA developers,
Could you please add PYNQ-Z2, ultra96 and zcu104 support?
Since these platforms are more cheap and easy to get for community.
Thank you very much.
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Hi FINN Team,
I am currently working on a project that is interested in recreating the quantized .onnx file used for the ResNet-50 FINN example here:
`https://github.com/Xilinx/finn-examples/tre…
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Hi,
I tried to connect to pulpissimo via jtag using openocd, but always get this error:
![398418445_209285052150728_6382659880394201287_n](https://github.com/pulp-platform/pulpissimo/assets/70802909…
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Hello,
I am trying to generate a bitstream directly for the ZCU104. However, when I checked the generated HLS project found out that:
1- There is no AXI bridge.
2- there is no TCL script to gener…
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Hello,
I have a project implemented using OpenCV and caffe packages. It is a classification project. I have trained the model using LeNet. Now I want to port it to the FPGA for which I want to conver…
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看到作者分享了在zcu104上部署yolov5非常激动,想请问一下作者能在领航者zynq7020上实现部署么,改进过的yolov5s,FLOPs减少了50%,暂时不考虑速度的话能实现部署么