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pulp-platform
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pulpissimo
This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
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Correct way to use L2_PRIV0 and L2_SHARED naturally
#427
2080fresh
opened
1 month ago
0
How to write CSR_DPC register in GDB ?
#426
rtspk
closed
1 month ago
0
How to read CSR_DPC register in GDB ?
#425
rtspk
closed
2 months ago
1
Version of Mentor Questa Sim
#424
NicholasLimJT
opened
2 months ago
0
How to program multiple cores using openocd
#423
rtspk
closed
1 month ago
0
HOW TO IMPLEMENT DOUBLE PRECISSION FPU SUPPORT FOR PULPISSIMO?
#422
LatifAkcayGithub
opened
2 months ago
0
UVM_ERROR reporter [CORE_TRACER 992]
#421
2080fresh
opened
2 months ago
0
PULP FreeRTOS on v7.0.0 ?
#420
Julien2109
opened
2 months ago
0
Unable to read GPIO as input
#419
Julien2109
closed
1 month ago
4
UART not working
#418
RenatoBelmonte
closed
2 months ago
3
illegal instruction error when during simulattions.
#417
zenon4689
opened
3 months ago
0
Rewrite README.md
#416
bluewww
opened
4 months ago
1
Michaero/pulpissimo v8 dev
#415
micprog
closed
4 months ago
0
Open OCD Simple Runtime
#414
rtspk
opened
4 months ago
0
Slack violation in Vivado synthesis for zcu-102
#413
RenatoBelmonte
opened
5 months ago
0
Can we integrate Vivado HLS generated IPs with floating point computations with PULPissimo ? Has anyone tried it ?
#412
Devansh1908
opened
5 months ago
0
riscv-013.c:1485 examine(): Debug Module did not become active. dmcontrol=0x0
#411
l1onog
closed
5 months ago
0
Getting an Idea related to Transmission on TX Port When Sending RX-Related Commands in PULPissimo's SPI Peripheral
#410
kasunb-accelr
opened
6 months ago
1
No output on minicom on running hello application for zedboard fpga
#409
zealshah29
closed
5 months ago
4
Can pulpissimo deploy DNN?
#408
l1onog
opened
7 months ago
0
Datasheet is not completed for uDMA SPI Command list
#407
kasun-buddhi
opened
8 months ago
0
are there any simulation models for SPI peripheral?
#406
kasun-buddhi
opened
9 months ago
1
Failed to connect to pulpissimo via jtag
#405
cern143
opened
9 months ago
1
VSIM_PATH and missing vectors dir?
#404
lmg260a
opened
10 months ago
0
I2C stuck at write stage, scl/sda pins never triggers
#403
Najah-Nasir
closed
10 months ago
0
Can Questa*-Intel FPGA Standard edition be used for RTL simulation ?
#402
haresh-seenivasagan
opened
10 months ago
1
frep-loop:Cannot select: intrinsic %llvm.riscv.frep.infer
#401
zhayongquan
opened
11 months ago
4
problem with vivado for windows
#400
RQiand
opened
11 months ago
9
Error connect openocd to debug pulpissimo
#399
namnguyen269
opened
11 months ago
1
latest SW support for pulpissimo
#398
akifejaz
opened
11 months ago
4
AXI exclusive write fails after regular write from reserving manager
#397
maxbjurling
closed
12 months ago
1
Halting the core for a few cycles and bringing it back to run
#396
prajwalkashyap
closed
1 year ago
0
Error on synthesis and bitstream generation
#395
xzj478
closed
1 year ago
0
Testbench for UDMA perripherals
#394
Ragineeiitb
opened
1 year ago
0
facing issues in make build step
#393
gagana-05
closed
1 year ago
0
Failed to access Library 'work' at 'work' while running Hello test
#392
anmol109
opened
1 year ago
2
Problem with integration of cv34e40p core: external interrupts (breaks freeRTOS port)
#391
kangoojim
opened
1 year ago
0
pulp-runtime vs pulp-freertos
#390
Wen-Sheng
opened
1 year ago
0
Has anyone implemented pulposimo on fpga and printed it out for helloworld?
#389
gyx3598
opened
1 year ago
2
Bitstream Generation Error
#388
Simon149
opened
1 year ago
3
OpenOCD Error: Debug Module did not become active. dmcontrol=0x0
#387
ivanhira
closed
1 year ago
4
UART module does not work when flash.bin generated from qspi_stim.slm by plp_mkflash.py is used.
#386
yadibelli
closed
1 year ago
3
Compile simulation model on Rocky Linux 8.7 (Green Obsidian)
#385
alruppin
opened
1 year ago
1
There was an error in the compilation of pulp-runtime examples. Is this the problem with the gcc compiler? Or is there a problem with my Centos7 environment?
#384
gyx3598
closed
1 year ago
7
I can't get tests. The git clone needs a password. What should I do?
#383
gyx3598
closed
1 year ago
2
PULP_LDFLAGS += -nostartfiles -nostdlib
#382
aledolme
opened
1 year ago
6
Latest Pulpissimo RTL doesn't fit the nexysA7-100T FPGA
#381
Ahmed1Zaky
opened
1 year ago
2
Zedboard running script is missing
#380
gyx3598
closed
1 year ago
1
Compile pulpissimo on zcu104 board:Timing constraints are not met
#379
alruppin
opened
1 year ago
14
Integrate Peripheral Event Linking System
#378
meggiman
opened
1 year ago
0
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