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Two problems:
1. The rounding mode, which is round to nearest even, in the functional model and RTL does not match. See: https://buildkite.com/stanford-aha/lassen/builds/109#712c5179-b555-4ddb-8fd3-6…
Kuree updated
5 years ago
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**Type of issue**: feature request
**Impact**: API addition (no impact on existing code)
**Development Phase**: request
**Other information**
**If the current behavior is a bug, p…
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Author Name: **Todd Strader** (@toddstrader)
Original Redmine Issue: 1490 from https://www.veripool.org
Original Assignee: Todd Strader (@toddstrader)
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Jumping off from here:
https://www.…
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It would be nice to have a way to visualize our pipeline, along with events. Currently, we have a few tracers printing logs (Calculator and CCE), but having a way to look cycle by cycle at what's hap…
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I wanna derive a rising edge event from the Clock() as below:
```scala
class RisingEdge () extends Module {
val io = IO (new Bundle {
})
val ev = Clock().asUInt //
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The repo "https://github.com/farshad112/ring_oscilator" contains verilog and systemverilog code.
The topics are managed as verilog, systemverilog-simulation and ring-oscillator. There is a single ru…
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ModelSim PE Student Edition is only available for Windows.
I couldn't find a (free) ModelSim setup file for Linux except ModelSim-Altera Edition. Is it OK to use it?
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As discussed I've taken a bit of time to create an initial classification hierarchy for LibreCores. I'm not sure yet where we'll hit a sweet spot between details and abstraction. Unless someone has st…
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i am trying to create an ip core with vivado of the ariane cpu but i am getting strange errors regarding - among others - the following code segment:
```
AXI_BUS
#(
.AXI_ADDR_WIDTH (…