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Should it build on 32 bit?
When I try on Ubuntu 14.04.5 LTS 32 bit the build fails.
I do this:
```
git clone https://github.com/riscv/riscv-qemu
cd riscv-qemu
git submodule update --init pixman
…
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Hi,
I was using the RISCV built GCC toolchain several months ago (which is based on GCC 6.1.0 version). Recently I have upgraded my database and use the latest built GCC toolchain (which is based …
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Hi Everybody,
I wanted to install freedom-s-sdk to work on PULPino simulations.
I have downloaded ZIP file from github and could see sub folders data missing.
Can you tell me ho…
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Hello,
I built the complete Linux environment by following the steps provided in this as well as the ones given in riscv-tools repository. I did the following steps.
1. Built the busyb…
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Test case
https://uclibc.org/~kraj/riscv-linker-test.tar.bz2
Fails to link
```
$ /opt/riscv/bin/riscv64-unknown-linux-gnu-gcc nss.c -lnss3 -L. -Wl,-rpath-link .
/opt/riscv/lib/gcc/riscv64-unk…
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Hi,
I have generated the verilog RTL for the Freedom E300 Chip. I would like to run an application on this RTL.
Is there a testbench available that would take the application as input and run it on …
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If we do make CROSS_COMPILE=riscv64-unknown-linux-gnu- ARCH=riscv vmlinux
it is failing with the error message
CC drivers/tty/serial/earlycon.o
drivers/tty/serial/earlycon.c:30:10: fatal…
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Hi SiFive's expert,
$ make -f Makefile.e300artydevkit verilog
When I adding generated verilog code to Vivado 2016.4 and synthesis it encounter error ,please tell me how to fix it. Thanks~
![s…
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I am having a whole lot of trouble finding a working combination of hardware and SD card image for the u500 on a VC707. By way of a sanity check, I am trying to get vanilla hardware and software to bo…
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We are trying to build the tool chain without the support of compression ISA set.
We did the following changes in the different files for this purpose:
a) In the Makefile @ freedom-u-sdk director…