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I want to increase the ariane core frequency ... How can I do that?
what is the max frequency reachable ?
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Hi,
I am trying to load a compiled ariane-sdk based vmlinux to a FPGA (ROM built with ariane.dts) via GDB. But the physical memory address on FPGA is 0x2_0000_0000. I wonder where & how do I chan…
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The riscv-gnu-toolchain repo commit that is checked out when running `piton/ariane_build_tools.sh` (which in turn calls `piton/design/chip/tile/ariane/ci/build-riscv-gcc.sh`) is from 2017. Some git s…
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When I tried to execute the test2.py, I get the following error.
MacroPlacement/CodeElements/FormatTranslators/test/LefDef2ProtocolBufferFormat/rtl_mp/ariane.hgr.io does not exist!!!
Also, I am…
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The CVA6 uses the following defines (used in ifdef/ifndef statements):
- DROMAJO
- FIRESIM_TRACE
- FORMAL
- INSTR_TRACER_IF_SV
- PITON_ARIANE
- SYNTHESIS
- VERILATOR
- WT_DCACHE
Similar t…
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### Is there an existing CVA6 bug for this?
- [X] I have searched the existing bug issues
### Bug Description
Hello,
I notice that in the cvxif.pkg, the **X_NUM_RS** is assign by **NR_RGPR_PORTS*…
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![image](https://cloud.githubusercontent.com/assets/2939098/22402291/0e85ba24-e5bf-11e6-98f2-658b5ceaa6c5.png)
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```
tansell@tansell-glaptop:~/github/PrincetonUniversity/openpiton$ source piton/ariane_setup.sh
----------------------------------------------------------------------
openpiton/ariane path setu…
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Hi,
On Genesys2 with MIG with AXI interface:
Discussed with Jon on problem of AXI address from NoC with UART boot option. As per his suggestion, It seems on this line, for ariane, it might to be s…
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Thank you! Is there a demo showing how to add new peripheral? Such as Gpio.