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Not an issue as such, just has anymore work been done on the core? I know e've limted things to try on it, but would be nice to see it finished one day. Thsnks.
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I'm using Verilator as part of a software for teaching digital design with the help of SystemVerilog, and we expect our students to not use any kind of inline logic net initialization. Shown in the e…
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Google is developing a SystemVerilog linter and code formatter called Verible. You might find it useful.
Some links include;
* https://github.com/chipsalliance/verible
* https://chipsalliance.g…
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I found that VNC needs the following to work:
Instead of
`docker run -it -p 80:80 --user $(id -u):$(id -g) -v $DESIGNS:/foss/designs efabless/foss-asic-tools:latest bash`
one needs to run
`…
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Hi, Alex
Can Axi-interconnect be used in ASIC? And I want to apply it to a school teaching project.
Thanks,
Tuuyii
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Flow fails with FP_SIZING=relative and FP_CORE_UTIL=30%. Other configurations were also tried but hardening failed for all. Configuration trials can be seen in openlane/sha1_top/config.tcl (https://gi…
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I was wondering if theres a way to make this run on an ASIC bitcoin miner.. I just wanna see how many kets can it run on an ASIC... if tgeres a way please let me know
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Get in touch with parties that contribute to Decred infrastructure but don't talk much with the community. Let them be known and get some credit.
* ASIC manufacturers
* VSP operators
* PoW pool o…
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We now have two ways of clock-gating a register, a `seq.compreg.ce` and `seq.clock_gate`+`seq.compreg`. Is there any merit to having both, or should `seq.compreg.ce` be removed in favor of the latter …
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Hi, I generated a verilog module for the litedram core and now I want to simulate it as as ASIC design, basically I am trying to dummy out those interfaces with FPGA.
Existed bench are all FPGA bas…