issues
search
alexforencich
/
verilog-axi
Verilog AXI components for FPGA implementation
MIT License
1.45k
stars
438
forks
source link
issues
Newest
Newest
Most commented
Recently updated
Oldest
Least commented
Least recently updated
it seem like axi_adapter not support outstanding transfer
#83
DV-Carium
opened
1 week ago
0
axil_fifo
#82
0TulipRose0
opened
1 month ago
1
`axi_dma_wr` does not respect TKEEP
#81
KireinaHoro
opened
1 month ago
1
axi_dma_wr seems to give done status before fully writing to DDR?
#80
abarajithan11
opened
2 months ago
6
Parameters not passed on to axi_crossbar_wr and axi_crossbar_rd in axi_crossbar.v
#79
RiceShelley
opened
3 months ago
0
Q: DMA, desc_len VS tlast in axi_dma_wr
#78
abarajithan11
opened
4 months ago
3
Performing multiple beat transfer
#77
ManjunathKalmath
closed
4 months ago
14
about AXI DMA
#76
zengzhengqi0524
opened
4 months ago
2
cocotb makefile
#75
ManjunathKalmath
closed
4 months ago
2
About AXI_FULL_CDC
#74
LZR1567
opened
6 months ago
2
about axi_ram
#73
nViol3t
opened
6 months ago
2
AXI_Register hangs when SIM=verilator
#72
ManjunathKalmath
closed
6 months ago
3
Failed to run test for AXI RAM with DATA_WIDTH=64 and ADDR=64
#71
ManjunathKalmath
closed
7 months ago
4
About the solution for deadlocks
#70
omeag
opened
7 months ago
14
about tb
#69
Unicorn619
opened
7 months ago
1
About width missmatch
#68
a60626316
opened
7 months ago
2
Timing issues with `axi_dma_wr`
#67
KireinaHoro
opened
8 months ago
0
Axi DMA consistently returns DECERR
#66
EnricoGiordano1992
opened
8 months ago
6
Will unprocessed awvalid signals be stored in AXI Crossbar?
#65
omeag
opened
8 months ago
6
Q: is there any component for read data out of standard ram/fifo and then transfer the data to axi master
#64
constant007
opened
9 months ago
4
about axi_ram design specification
#63
Maani02
opened
9 months ago
0
Add explicit python3 prefix to all python paths in test suite
#62
dbarrie
opened
10 months ago
0
Add explicit python3 prefix to all python paths in test suite
#61
dbarrie
closed
10 months ago
0
Q: Do axi_dma_rd and axi_dma_wr support out of order transactions?
#60
abarajithan11
opened
11 months ago
2
about AXI_VFIFO
#59
Monster-Kee
opened
1 year ago
3
I met a question about simulation, please some one help me?
#58
OldTomCrazyCode
closed
1 year ago
2
awready and wready set high in master without slave value
#57
sazam0
opened
1 year ago
0
Why assume packet smaller than max burst size when AXI_MAX_BURST_SIZE >=4096?
#56
qiweiii-git
closed
1 year ago
10
axi_interconnect Synthesis
#55
GGbang2
opened
1 year ago
1
AXI Lite interconnect in N to 1 configuration
#54
Twistix
opened
1 year ago
2
AXI Reset Signal
#53
mkokki
opened
1 year ago
0
About priority_encoder
#52
GGbang2
opened
1 year ago
4
AXI interconnect
#51
ilamparithy01
opened
1 year ago
2
Documentation for axil_interconnect
#50
catkira
opened
1 year ago
3
Fix AXI_ADDR_BIT_OFFSET and AXIL_ADDR_BIT_OFFSET part select
#49
AlexLao512
opened
1 year ago
6
AxiLiteMaster hangs with Verilator
#48
catkira
opened
1 year ago
14
WIP: Verilator Compatibility
#47
benreynwar
opened
1 year ago
0
axil_adapter_wr : Modelsim error "part select is reversed"
#46
peioazk
opened
1 year ago
8
tb simulation failed
#45
nashsrg
opened
1 year ago
2
AXIL crossbar doesn't support M_ADDR_WIDTH < 12
#44
martin-tanguay
opened
1 year ago
8
Does the AXI bus adapter support the downsizer from 256bits to 8bits?
#43
chengquan
closed
1 year ago
12
add option for initialization file for RAM
#42
bunnie
opened
1 year ago
0
fix numerical overflow in bit shift operation
#41
bunnie
opened
1 year ago
0
Disable verilator lint warnings
#40
zhizhenzhong
closed
1 year ago
0
fix vivado synthesis problems in axil_reg_if_wr.v
#39
jameyhicks
closed
1 year ago
7
Parametrization doesn't work correctly in testbenches
#38
vkomenda
closed
2 years ago
2
axi_adapter: fix compilation with verilator
#37
sergachev
closed
2 years ago
7
axil_ram. How to adjust rvaild delay.
#36
cjhonlyone
closed
2 years ago
0
question: how to read this syntax?
#35
hughperkins
closed
2 years ago
2
Circular logic in axi_crossbar
#34
MikeWalrus
opened
2 years ago
0
Next