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I've tried Digital looking for a more modern version of Logisim and that's how I ended up here. This is my feedback after trying my usual workflow for a short time. I hope you don't find this post too…
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This is based on the review with @hacst on the phone.
Our goal is to keep the backend frontend interface as simple as possible, with the following design rationals:
- new functionality in the fronten…
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- [x] I have read [CONTRIBUTING.md](https://github.com/idris-lang/Idris2/blob/main/CONTRIBUTING.md).
- [x] I have checked that there is no existing PR/issue about my proposal.
## Summary
Since …
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Basic idea is to create something low-level, like LLVM Bitcode or WebAssembly, to create the HDL compilers emit the code in this format, which will be fed to the routers/synthesizers after. This will …
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I wonder whether there is some extensive roadmap or at least ambitious ideas how to further develop this neat language?
I have some crazy ideas but I'd first want to know about existing plans :wink…
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This is tracking the next piece of https://github.com/dotnet/aspnetcore/issues/27576. **(Pointing out that this issue has additional 20 reactions)**
We want to provide the ability for circuits to b…
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I see in the 'expansion.md' file that SBUS is read on the CVBS pin.
Does it also need ground?
The document also says the signal needs '0x01 in first byte'
How do I know if my SBUS signal has the …
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I've ended up having this kind of design pop up several times where, essentially, I want to structure my overall project into two components:
1) A **shell** for my FPGA board, that abstracts out …
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I wonder what the future and the roadmap looks like?
I have also some (very) crazy ideas but I'd first like to learn about the goals and roadmap if any :wink:.
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I have started to work on a better version for my type-based waveform viewer for [Tydi](https://github.com/ccromjongh/Tydi-Chisel) and Chisel-related projects (Tywaves).
My chisel fork: https://git…