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**Describe the bug**
HF iclass sam gives a SAM select Failed error when attempting to read a iclass legacy tag using a HID sam chip with a SIM to Smartcard adapter
**To Reproduce**
Steps to repr…
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I know this may sound like something too much to be done in the near future, but have you considered utilizing cloud FPGA services to achieve more parallel speedups? Do you have any experience in this…
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Is there any documentation about the `-fintelfpga` flag ?
I've tried to build the simply SYCL application from [the getting started page](https://github.com/intel/llvm/blob/sycl/sycl/doc/GetStarted…
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**Is your feature request related to a problem? Please describe.**
The `m65` command has a "screenshot" feature that operates by using the serial debugger to read and interpret VIC register state, re…
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Hey there,
I switched over to using the latest interim version for performing this, and my FDSKey is at v1.3. (I opted to use the interim version because I kept getting a no power error message, bu…
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So we have hardware for different FPGAs.
If we send the wrong bitfile to the board, it will not configure, right? How about we write board information to its onboard flash, and our program checks the…
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Hello I was wondering, is it feasible to add the "H" extension for hypervisors to the 64bit core? Or would that require too much re-engineering of your existing design ?
I am asking because hardwa…
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Hi! Friends, I am measuring the performance of XDMA on the Z19-P board, PCIe Gen4x16 (the IP core only supports Gen3x16) - and I can't reach the theoretical speed of at least 12 GB/s, but i get only *…
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**Overview:**
While working with the TEB0707-02 FPGA Carrier Card and integrating the debayer module for raw to BGR conversion, our team encountered pinout inconsistencies across CRUVI sites and diff…
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# Summary
Hi, I'm trying to compile for FPGAs in the Intel Devcloud. The problem is that I'm getting an error when I try to compile for hardware, it works well for emulator.
# Steps to reproduce
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