-
Okay, so the Verilog is in rough shape for a few reasons. The biggest is that it was clearly written as Jon was learning (
-
## Hardware and software
- **mt32-pi version:** v0.10.0
- **Raspberry Pi model:** 4 Model B
- **MIDI host:** MacBook Pro mid-2015 over LAN/WLAN (macOS 11.4)
## Bug description
I can get the…
-
## Hardware and software
- **mt32-pi version:** v0.10.0
- **Raspberry Pi model:** Raspberry Pi 3 Model A+
- **HATs:** MiSTer mt32-pi
- **USB devices:** None
- **MIDI host:** MiSTer USER I/O por…
-
The USB device (usbdev) has a somewhat special IO setup which complicates the top-level integration in several ways:
1. usbdev features both differential and single-ended IOs. Using a control regis…
-
## Hardware and software
- **mt32-pi version:** 0.11.0
- **Raspberry Pi model:** Raspberry Pi 3 Model A+
- **HATs:** MiSTer mt32-pi hat
- **USB devices:** None
- **MIDI host:** MiSTer USER …
-
Hello,
This is obviously a joke. I don't know what effort it would take to build such a device.
Congratulation on your impressive work.
Best regards.
ghost updated
2 years ago
-
Hello
Problem:
I target a design for FPGA. I have know a couple of verilog module, build on a bottom-up approach.
I face strange behaviour when running the application : sound synthesizer . And I wa…
-
## Hardware and software
- **mt32-pi version:**
v0.10.3
- **Raspberry Pi model:**
Raspberry Pi 3 Model B+_
- **HATs:**
Pi-MIDI
- **USB devices:**
None
- **MIDI host:**
38…
-
## Hardware and software
- **mt32-pi version:** v0.10.0
- **Raspberry Pi model:** Model 3A+
- **HATs:** None
- **USB devices:** None
- **MIDI host:** Pentium II with Yamaha YMF719E-S chip (Audi…
-
Please investigate settings for XPROP at Xcelium. There is an infinite loop using Xcelium with enabled XPROP switch (default value) which is not seen using VCS. Solution for this was adding switch -xf…