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The description found in this xml file (from Infineon) involves custom variables and tables which cannot be taken into account properly (both in conduction and switching losses):
* custom variables…
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Beginning from 2022-09 I am not able to execute JUnit Plug-in Tests. Works fine with 2022-06 IDE.
(Update: issue still there in 2023-06)
My Setup:
* Tests provided within fragment project
* Targ…
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Implement a feature to the Sidebar that allows the user to collapse and expand the Sidebar.
Design reference: https://www.figma.com/design/zPvPwPgb4EsYFXKC2nhzSG/Infineon-DDS-%7C-Main?node-id=23998-1…
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### Reproduction steps
```bash
$ python3 out/infineon-psoc6-lock/chip-psoc6-lock-example.flash.py -h
usage: chip-psoc6-lock-example.flash.py [-h] [--verbose] [--erase] [--application FILE] [--verify…
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Looks like HyperRAM 3.0 is upcomming:
https://www.infineon.com/cms/en/product/memories/psram-pseudostatic-dram/
We are going to get twice wider data bus width, i.e. 16 bit at 200MHz = 800Mbit/s pe…
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**Prerequisites**
Can you reproduce the problem reliably?
yes
Did you check current release notes for known issues?
yes
If this is not the latest release, have you checked newer releases?
*…
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### Reproduction steps
See https://github.com/project-chip/connectedhomeip/actions/runs/6419947084/job/17430925859?pr=29582 from turning on `-Wundef`. The errors look like this:
```
INFO ../../…
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Similar to the TriCore implementation, find the DWARF Register number -> Register name mapping from the architecture's ABI document.
ch4.5.1 https://www.infineon.com/dgdl/Infineon-TC2xx_EABI-UM-v02_…
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### Build issue(s)
The lock app is built including the ICD management cluster by default, but we are not enforcing it to be build as an ICD, meaning that it does not include the ICD manager source se…
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sad face https://www.findchips.com/search/MCz33800
https://github.com/rusefi/rusefi/wiki/Infineon-chips-comparison
![image](https://user-images.githubusercontent.com/48498823/182018651-ccc9ca02-…