-
# Sighting report
When loading a logical volume store, spdk reads extent pages 3 time for a blob:
1. spdk_lvs_load calls spdk_bs_load which iterates all blobs and read blob extent pages.
2. load_…
-
The CI has been failing on various LVS jobs for over a year now.
Is this expected or is it a regression? And what can we do to fix it?
-
`Netgen 1.5.265`
In verilog, top level assign statements can be used to effectively short port nets. magic can extract multiple ports on the same physical net by placing a virtual resistor between …
-
**Is this a bug report or feature request?**
* Bug Report
**Deviation from expected behavior:**
Ceph v17.2.7 is failing to start OSDs in certain configurations.
- LVs as seen [here](https:/…
-
Hi,
I ran `PLIER` and `delayedPLIER` using the same parameters and the same SVD (calculated using `BiocSingular::runRandomSVD()` ).
The mean correlation of both Z matrices is around 0.8, and the…
-
openlane based notebooks like https://github.com/chipsalliance/silicon-notebooks/blob/main/xls-adder-openlane.ipynb seems to be failing LVS with the following error:
```
Cannot find cell __adder__ad…
-
Hi Tim, when hardening the user project wrapper in openlane I get an LVS issue with logic analyser pin not being found.
[multi_project_harness.lvs.log](https://github.com/RTimothyEdwards/netgen/fil…
-
In a typical IC design, different VSS nets are used in different areas for blocks requiring isolation (e.g., digital blocks vs. analog blocks), leading to p-taps shorting these VSS nets via the (commo…
-
This also might be useful.
Seems to be a nice option instead of poor man DNS short TTL round robin;
See
http://kaivanov.blogspot.nl/2013/01/building-load-balancer-with-lvs-linux.html
http://www…
-
One of my steps has an unconnected input, due to an `extend_inputs` command in the construct.py without an accompanying `g.connect` for the step that is supposed to supply the input. In the example be…