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### Current Behavior
The `decode` function always uses `shamt6` as the shift amount for "shifts by a constant" instructions (SLLI, SRLI, SRAI), where `shamt6` refers to the lower 6 bits of the imme…
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- [ ] Verificar instrucoes RV32I
- [x] AUIPC: Necessário somar o PC, mudar o ALUControl para somar
- [ ] JAL, JALR
- [ ] Store/load byte/half
- [x] Set less than
- [ ] Verificar instrucoe…
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`I-RF_x0-01` has trouble building with what looks like a sign extension issue:
```
ERROR: /usr/local/google/home/drewmacrae/opentitan/third_party/riscv-compliance/BUILD:9:21: Compiling riscv-test-su…
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I am using RISCV-ISAC to generate the add instruction coverage. I found that some checkpoints in CGF are 0, but it is obvious from the assembly file that this constraint is satisfied. Is this normal?…
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圧縮命令が未実装なため、rv32ima toolchain を使用したいが、rustup には用意されていないため rv32i で動作するようにする。
アトミック命令が使用できないため、machine::stdio::UARTBuffer 関連で、Mutex を使用しないようにする(シングルスレッドなため、とりあえずグローバルでも大丈夫なはず)
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This strictly isn't a problem with picorv32, but with the RISCV toolchain. However I'll start here as I suspect many might hit this from here.
Environment: a fully updated Ubuntu 21.10/AMD64
Co…
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Should the GUI prevent the user from configuring illegal combinations of RISC-V architecture, abi and floating point etc.?
Or maybe it is deliberately permissive for simplicity and depends on the com…
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So, this is a pretty big challenge I think....
The iCE40 1K has the following resources;
* 1280 Logic Cells
* 64kbits Embedded RAM bits
* 1 PLL
However, there might be hope, your stats …
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The variable 'xlenlim' referenced in the abstract combination of a few bitmanip instructions within the configuration files rv32i_b.cgf, rv32e_b.cgf, and rv64i_b.cgf appears to be "not defined", leadi…
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Recently when I compile the RISC-V toolchain, I cannot get caravel_board examples to compile unless I modify the compile line to change `-march=rv32i` to `-march=rv32i_zicsr`.
Apparently this is be…