SpinalHDL VexRiscv issues

SpinalHDL / VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

MIT License

2.52k stars 420 forks source link

issues

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add Murax config with native jtag based on the docs

#434 goekce closed 2 weeks ago
3
Fix undriven signal

#433 7FM closed 3 weeks ago
3
Verilator requires at least c++14

#432 goekce closed 1 month ago
1
Verilator expects `-std=c++14`

#431 goekce closed 1 month ago
1
compiling CFU demo configurations results in : java.lang.Exception: Missing inserts : LEGAL_INSTRUCTION"

#430 jahagirdar closed 2 months ago
1
SiFive GCC link in Readme.md is dead.

#429 jahagirdar closed 2 months ago
1
What tools are supported

#428 SeanGan233 closed 2 months ago
2
DBusSimplePlugin: don't force SEL to 1111 on read.

#427 kivikakk closed 2 months ago
2
DBusSimplePlugin's Wishbone support forces 32-bit reads

#426 kivikakk closed 2 months ago
3
build.sbt: Bump SpinalHDL and Scala version

#425 dnltz closed 3 months ago
1
Instruction that need Multiple cycles for execution

#424 karegoud closed 2 months ago
3
Tunneled EmbeddedRiscvJtag without TAP

#423 craigjb closed 3 months ago
1
Multiple register read from Register file

#422 xavier-design closed 3 months ago
3
GenFullWithOfficialRiscvDebug failed

#421 Logiase closed 3 months ago
1
VexRiscv for custom processing in memory instructions

#420 neha2351 opened 3 months ago
2
Data buffer

#419 xavier-design closed 3 months ago
6
new custom instruction in vexriscv

#418 Chaitanya-kumar-Y closed 4 months ago
11
Add Zkn variant of AES plugin

#417 bunnie closed 4 months ago
1
machineCsr test failing

#416 jbrown11111 closed 4 months ago
2
Internal timer implementation

#415 juliaazziz closed 5 months ago
1
how to send data serially using apbbus when using murax soc

#414 karegoud closed 4 months ago
4
Fix Mhz -> MHz in README, comments and Dhrystone benchmark output

#413 mrcmry closed 5 months ago
1
Wrong speculative execution when conditional branch argument is in TCM address range

#412 vianney closed 5 months ago
1
Help for custom instruction

#411 ztachip closed 4 months ago
7
Exposed write mask on default iBus

#410 MrJake222 closed 6 months ago
1
default bus doesn't expose write mask

#409 MrJake222 closed 6 months ago
0
rdcycle and rdinstret instructions not working

#408 MrJake222 closed 6 months ago
2
VexRiscV shift bus fail

#407 MrJake222 closed 6 months ago
3
AxiCrossBar with Standard Axi4 Interface in Briey

#406 ic-hjx opened 7 months ago
15
How to only modify certain one reset kind of specific Reg in vex core.

#405 littlezpf666 closed 7 months ago
0
How to only modify certain one reset kind of specific Reg in vex core.

#404 littlezpf666 opened 7 months ago
1
About the Csr registers in Vexriscv

#403 ic-hjx closed 7 months ago
2
How to use printf function?

#402 Guochen-Shine closed 7 months ago
10
Problem about how to compile the software that can be used in Vexriscv with FPU

#401 ic-hjx closed 7 months ago
10
Problems with adding FPU in Briey

#400 Guochen-Shine closed 7 months ago
5
Handle `ERR` in `toWishbone`

#399 martijnbastiaan closed 8 months ago
2
Exit cycle accurate simulation

#398 ashuthosh-mr closed 1 week ago
1
Fix SMP compile-time error when disabling supervisor option

#397 cherrypiejam closed 8 months ago
1
Debug instructions executed twice

#396 patstew closed 9 months ago
5
Compile C code and run bare metal cycle accurate simulation

#395 nachiket opened 9 months ago
3
Improved the paragraph about available configurations.

#394 PythonLinks closed 9 months ago
1
EU Funding

#393 PythonLinks opened 9 months ago
3
FPU plugin to GenFull.scala

#392 ashuthosh-mr closed 9 months ago
3
Data Stream in/out SoC <-> FPGA

#391 lk-davidegironi opened 10 months ago
6
Adding VexRiscV as a dependency

#390 DanielMadmon closed 9 months ago
2
DE0-Nano Board with VexRiscV: IO and Fit Design Issues Including Specific Command Used

#389 Tahamermer opened 10 months ago
3
Perf counters

#388 jjjt-git closed 8 months ago
9
Instructions to save/restore register to stack is taking 2 clock each

#387 ztachip closed 8 months ago
12
Add mill to compile and test VexRiscv

#386 davine47 closed 11 months ago
1
Fetch dosen't performed correctly in the simulation of Murax SOC.(+Custom instructions are executed in unexpected time.)

#385 nohahanon opened 11 months ago
1