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SpinalHDL
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VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
MIT License
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debug
#384
chshux
opened
11 months ago
1
Regarding the result of dhrystone with TCM
#383
piondeno
closed
11 months ago
6
CPU exception signal
#382
snowprogrammer
closed
11 months ago
3
EmbeddedRiscvJtag synthesis issue
#381
gregdavill
closed
6 months ago
7
Murax XIP compile issue
#380
lk-davidegironi
opened
1 year ago
11
Transfer data double times
#379
snowprogrammer
closed
1 year ago
1
Rename `PmpPlugin -> PmpPluginNapot`, `PmpPluginOld -> PmpPlugin`
#378
lschuermann
closed
1 year ago
2
Fix ambiguous function call to bind()
#377
Tectu
closed
1 year ago
1
Combinatorial loop with AhbLite3Decoder
#376
patstew
closed
1 year ago
1
Add note about Verilator without GDB+OpenOCD
#375
widlarizer
closed
1 year ago
0
PmpPluginOld: fix NAPOT address calculation overflow issue
#374
lschuermann
closed
1 year ago
4
Scratchpad memory with cached IBUS and DBUS?
#373
piondeno
closed
1 year ago
15
Adding FPU to AHBLite3 config file
#372
vidushiy25
closed
1 year ago
8
Assertion when tracing the elaboration issue
#371
eruanno123
closed
1 year ago
5
Interface BSCAN2 with VexRiscv's JTAG
#370
ztachip
closed
1 year ago
3
MAC custom instruction implementation
#369
Shris7
closed
1 year ago
1
Read speed: dcache width impact 32bit vs 64bit
#368
pottendo
closed
1 year ago
10
sbt fail: [error] error while loading <root>, Error accessing... scalactic_2.11-3.2.5.jar
#367
pottendo
closed
1 year ago
4
Add missing parameter jtagHeaderIgnoreWidth
#366
robindust-ce
closed
1 year ago
1
Where are the CLINT and PLIC described?
#365
PedroAntunes178
closed
1 year ago
5
Unsupported compressed instruction on VexRiscvAxi4LinuxPlicClint.scala
#364
PedroAntunes178
closed
1 year ago
3
VexRiscvAxi4LinuxPlicClint not respecting the AXI protocol
#363
PedroAntunes178
closed
1 year ago
20
compiling verilog code in verilator by Verilator 4.216 2021-12-05 rev v4.216
#362
SoCScholar
opened
1 year ago
1
RiscV Counters
#361
jjjt-git
opened
1 year ago
1
Some documentation on Timer/interrupts
#360
Jupestrone
opened
1 year ago
1
A bug in https://github.com/SpinalHDL/VexRiscv/blob/master/src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala
#359
FvTao
closed
4 months ago
1
Hi,I have some trouble ,please reply me at your convenience
#358
siatzjs
closed
1 year ago
1
Dcahce single burst on AXI write
#357
hszilard13
closed
1 year ago
3
In configuration modified based on briey, the lw instruction cannot access the unaligned address
#356
LongStudy
closed
1 year ago
7
dev, sim: Error: fpga_spinal.bridge: IR capture error; saw 0x0f not 0x01
#355
likewise
opened
1 year ago
3
How to add I/Dcache support to MURAX
#354
LongStudy
closed
1 year ago
2
Error running MURAX on ARTY-A7 board and printing characters over Serial Port using println function
#353
LongStudy
closed
1 year ago
5
Custom Interruptions error and Selection of the 'A' instruction set
#352
joeljeanmonod-rgb
closed
1 year ago
1
How can with Murax soc connect a memory on apb bus?
#351
MartinaBarreiroGuerra
opened
1 year ago
3
Add cmd halfPipe function to DBusSimpleBus
#350
AdDraw
closed
1 year ago
2
SIMD_ADD custom instruction not working in C code
#349
tiagoasilva-meec
closed
1 year ago
1
How the Jtag works when I load the Program?
#348
xie-1399
closed
1 year ago
1
Briey on AHBL
#347
AdDraw
closed
1 year ago
6
Fuzzing VexRiscv
#346
TobiasKovats
closed
1 year ago
6
Predicted branch taken after compressed EBREAK
#345
patstew
closed
1 year ago
6
Does "MANAGEMENT" a customized INSTRUCTION?
#344
ZhengJuzhong666
closed
1 year ago
2
X over-propagation
#343
flaviens
closed
1 year ago
18
How to add a custom instruction that can read rd
#342
LongStudy
closed
1 year ago
8
Bug report: VexRiscv overcounts the retired instructions
#341
flaviens
closed
1 year ago
4
Bug report: VexRiscv raises an illegal instruction when writing to mcycle, mcycleh, minstret and minstreth
#340
flaviens
closed
1 year ago
3
Questions about the memory of the Murax SoC and the VexRiscv in general
#339
joeljeanmonod-rgb
closed
1 year ago
2
Adding 'C' extension to MyVexRiscv.scala
#338
FaizanAhmad626
closed
1 year ago
0
Cannot access medeleg and mideleg
#337
flaviens
closed
1 year ago
7
Bug report: Operations on floating-point registers should raise an exception when FS=0
#336
flaviens
closed
1 year ago
2
Bug report: Reading floating-point CSRs should raise an exception when FS=0
#335
flaviens
closed
1 year ago
3
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