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Requested:
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The [Yosys GHDL plugin](https://github.com/ghdl/ghdl-yosys-plugin) is still listed as experimental but is already very useful. For formal verification GHDL's support for PSL seems more extensive than …
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Hi,
First of all, thank you for the great job you've done on this extension. It is very pleasant to use it when you develop in VHDL.
I've a question:
Is it possible to have some features simila…
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The older Xilinx tools use the UCF file format.
The format is documented here - https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/cgd.pdf
http://xilinx.eetrend.com/files-eetrend-x…
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VHDL process details which were specified inside a process aren't in output.
Particularly global scope tags like \todo and self-written aliases get lost.
The attached example was generated with …
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**What is your question?**
I noticed that are hundreds of unit tests, but I wonder how much testing is performed at the "system" level, i.e. real world combinations of rules?
Is there any merit in…
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I am trying to run the example from the docs https://pyvhdlparser.readthedocs.io/en/latest/BlockStream/Usage.html
And I get an NoneType is not iterable error.
here is my code
```
from pyVHDLPars…
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When using universal-ctags as the default parser in gtags I get this warning:
```
Using configuration file '/Users/hisnawi/gitproject/gtags.conf'.
Using configuration label 'default'.
Using '…
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Hello, how could I use your schematic viewer to visualize diagrams of VHDL/Verilog hierarchical entities starting from source files?
Thank you and congratulations on your project.