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I gave been running stimulation by Verilator. The error like this
%Warning-CASEINCOMPLETE: ../../outdir/nv_full/vmod/nvdla/csc/NV_NVDLA_CSC_WL_dec.v:12633: Case values incompletely covered (example…
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I have a module `mod` which I instantiate with the instance name `top` in a Verilog testbench module `main`. When I display the module heirarchy/scope with `%m`, the output I expect from Verilog simu…
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NVDLA was open sourced around 7 years ago. During this time period, there are new ideas and design constantly proposed. For sure, those later designs must have something implemented in a better way th…
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Source:
https://raw.githubusercontent.com/varnishcache/varnish-cache/master/lib/libvmod_directors/vmod.vcc
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Hi,
when I look into ./hw/outdir/nv_small/vmod/include/hw/outdir/nv_small/vmod/include/NV_HWACC_NVDLA_tick_defines.vh
I see the following line
`include "NV_HWACC_common_tick_defines.vh"
But …
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IGRF-13 has been available for some time now. Any plans to integrate it into pyglow?
https://www.ngdc.noaa.gov/IAGA/vmod/igrf.html
Thanks.
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### Expected Behavior
Director reference counting should avoid use-after-frees
### Current Behavior
I believe there are still open races with our director reference counting
#### Simple di…
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@xdecock Would you mind explaining what the unimplemented constants below refer to? Some wider context would be really helpful.
https://github.com/xdecock/vmod-modsecurity/blob/9378bffe1b8214423625…
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In the Cache-Documentaion there is a broken link to X-Key.
https://github.com/dunglas/vulcain/blob/main/docs/cache.md
Broken in Master-Branch
https://github.com/varnish/varnish-modules/blob/maste…
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Hi,
When I try to do e.g.,
```shell
$ VASSAL.sh --load AfrikaKorps.vmod
VASSAL: File '[Ljava.lang.String;@1c93f6e1' of unknown type
VASSAL.launch.LaunchRequestException: File '[Ljava.lang…