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**Description**
I have built a linuxkit image that is an amalgam of the `examples/aws.yml` and the `examples/docker.yml` for the purpose of experimenting with various Swarm configurations. With t…
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**Current behavior**
- Bitstream programming must be done either via Vivado or Vitis/SDK
- Flash programming must be done by launching a Vitis/SDK run session
- Bitstream is part of the repository
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README mentions 13 mega-samples/sec over wifi and says ethernet is much faster -- what have you seen for continuous streaming rate over ethernet?
The docs for RP streaming server only promise 20MB/…
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Hi,
I am not sure if there is a better place to post this question. If so, please let me know and I will move it.
As the creator of www.pyrpl.org (DSP tools for test and measurement application…
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Would you mind publishing some FPGA resource usage and Fmax numbers and the configuration/part number used? I tried synthesizing (in Vivado) for various 7 series and Ultrascale parts, but could never …
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Hello Pavel,
Probably too early to say (??) , but will your different software remain compatible with the new RP announced on 22 November 2018 ?
see: https://www.redpitaya.com/n86/new-stemlab-sdr…
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Sometimes, when try to use two way transfer I get timeout error (in receive part). Also, I see that data correctly send out from DMA, but in some causes incorrect received (if set false on wait).
[t…
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Bonjour,
Je cherche a comprendre si avec l'image PlutoSDR "custom" que vous avez crée avec tous ces outils et scripts, il est possible d'utiliser mon PlutoSDR pour mesure la courbe de réponse e…
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Hi
Can you explain in detail how to give clk_in by using PS. Do I have to add Zynq processing IP into the design and then set clock. If yes how do I connect this zynq ps to rest of the design, or sim…
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Hi bperez77,
I am trying to install your driver for using with DMA on petalinux 2017.4 and run into some problems.
Here is what I have done:
```
root@zynq_petalinux:/lib/modules/4.9.0-xilinx-v20…